Law Hoi Ying. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 101-106). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- VLSI Design Cycle --- p.2 / Chapter 1.2 --- Physical Design Cycle --- p.6 / Chapter 1.3 --- Floorplanning --- p.10 / Chapter 1.3.1 --- Floorplanning Objectives --- p.11 / Chapter 1.3.2 --- Common Approaches --- p.12 / Chapter 1.3.3 --- Interconnect-Driven Floorplanning --- p.14 / Chapter 1.4 --- Motivations and Contributions --- p.15 / Chapter 1.5 --- Organization of the Thesis --- p.17 / Chapter 2 --- Literature Review on 2D Floorplan Representations --- p.18 / Chapter 2.1 --- Types of Floorplans --- p.18 / Chapter 2.2 --- Floorplan Representations --- p.20 / Chapter 2.2.1 --- Slicing Floorplan --- p.21 / Chapter 2.2.2 --- Non-slicing Floorplan --- p.22 / Chapter 2.2.3 --- Mosaic Floorplan --- p.30 / Chapter 2.3 --- Summary --- p.35 / Chapter 3 --- Literature Review on 3D Floorplan Representations --- p.37 / Chapter 3.1 --- Introduction --- p.37 / Chapter 3.2 --- Problem Formulation --- p.38 / Chapter 3.3 --- Previous Work --- p.38 / Chapter 3.4 --- Summary --- p.42 / Chapter 4 --- Literature Review on Bus-Driven Floorplanning --- p.44 / Chapter 4.1 --- Problem Formulation --- p.44 / Chapter 4.2 --- Previous Work --- p.45 / Chapter 4.2.1 --- Abutment Constraint --- p.45 / Chapter 4.2.2 --- Alignment Constraint --- p.49 / Chapter 4.2.3 --- Bus-Driven Floorplanning --- p.52 / Chapter 4.3 --- Summary --- p.53 / Chapter 5 --- Multi-Bend Bus-Driven Floorplanning --- p.55 / Chapter 5.1 --- Introduction --- p.55 / Chapter 5.2 --- Problem Formulation --- p.56 / Chapter 5.3 --- Methodology --- p.57 / Chapter 5.3.1 --- Shape Validation --- p.58 / Chapter 5.3.2 --- Bus Ordering --- p.65 / Chapter 5.3.3 --- Floorplan Realization --- p.72 / Chapter 5.3.4 --- Simulated Annealing --- p.73 / Chapter 5.3.5 --- Soft Block Adjustment --- p.75 / Chapter 5.4 --- Experimental Results --- p.75 / Chapter 5.5 --- Summary --- p.77 / Chapter 6 --- Bus-Driven Floorplanning for 3D Chips --- p.80 / Chapter 6.1 --- Introduction --- p.80 / Chapter 6.2 --- Problem Formulation --- p.81 / Chapter 6.3 --- The Representation --- p.82 / Chapter 6.3.1 --- Overview --- p.82 / Chapter 6.3.2 --- Review of TCG --- p.83 / Chapter 6.3.3 --- Layered Transitive Closure Graph (LTCG) --- p.84 / Chapter 6.3.4 --- Aligning Blocks --- p.85 / Chapter 6.3.5 --- Solution Perturbation --- p.87 / Chapter 6.4 --- Simulated Annealing --- p.92 / Chapter 6.5 --- Soft Block Adjustment --- p.92 / Chapter 6.6 --- Experimental Results --- p.93 / Chapter 6.7 --- Summary --- p.94 / Chapter 6.8 --- Acknowledgement --- p.95 / Chapter 7 --- Conclusion --- p.99 / Bibliography --- p.101

Este trabalho apresenta um gerenciador de ferramentas para projeto de circuitos integrados, o sistema TENTOS, agora desenvolvido para o ambiente MS-WINDOWSTM. O ambiente TENTOS é um sistema aberto, isto é, permite a fácil inclusão de novas ferramentas em tempo de execução do gerenciador, tornando-o desta forma sempre atual em relação as ferramentas existentes. Inicialmente será feita uma breve descrição de alguns dos gerenciadores existentes, tanto os desenvolvidos com finalidades comerciais como os do meio acadêmico Em seguida, será apresentado um histórico sobre a evolução do sistema TENTOS, da sua versão inicial até a sua versão atual. Em uma etapa seguinte será descrito o estado atual do sistema TENTOS, isto é, suas características principais a estrutura dos menus, os arquivos de configuração do sistema. como incluir novas ferramentas, arquivos de tecnologia, a configuração standard do sistema, quais ferramentas acompanham o TENTOS; como funciona a execução das ferramentas. Concluída a apresentação do sistema TENTOS, sendo apresentados exemplos que ilustram as etapas de desenvolvimento de um projeto de circuito integrado utilizando o sistema TENTOS. / This dissertation presents a tool mana ger for integrated circuit design, the TENTOS system, now developed for the MS-WINDOWSTM environment. The TENTOS package is an open system. that allows an eas y inclusion of new tools in the execution time of the manager, allowing an easy and constant updating of tools that are integrated into the package. Firstly, a short description of existing frameworks will be shown b y including commercial and academics systems. Secondly, a brief historical of TENTOS evolution system will be presented. Following thet description the present state of the TENTOS s ystem will be described which comprises: its main characteristics: the structure of menus; system configuration files; how to include new tools and technology files; the standard system configuration, which tools are available into the TENTOS and how they are executed. Finally some examples on how to use the TENTOS system will be shown.

Cheung, Cheuk Kit. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Abstract --- p.1 / 摘要 --- p.2 / Acknowledgements --- p.3 / Table of Contents --- p.4 / List of Figures --- p.9 / Chapter 1. --- Introduction --- p.12 / Chapter 1.1. --- Research Motivation --- p.12 / Chapter 1.1.1. --- Global and Intermediate Interconnects --- p.12 / Chapter 1.1.2. --- Constraints of Repeater Insertion Techniques --- p.13 / Chapter 1.2. --- Research Objective --- p.13 / Chapter 1.3. --- Reference --- p.14 / Chapter 2. --- Voltage Mode and Current Mode Circuits --- p.16 / Chapter 2.1. --- Introduction --- p.16 / Chapter 2.2. --- Voltage Mode Circuit --- p.16 / Chapter 2.3. --- Current Mode Circuit --- p.18 / Chapter 2.4. --- Power Consumption --- p.19 / Chapter 2.5. --- Latency --- p.20 / Chapter 2.6. --- Summary --- p.20 / Chapter 3. --- Transmitter Design --- p.22 / Chapter 3.1. --- Introduction --- p.22 / Chapter 3.2. --- Multi-level Signaling --- p.22 / Chapter 3.3. --- Gated Current Mirror --- p.23 / Chapter 3.4. --- Power Consumption --- p.24 / Chapter 3.5. --- Summary --- p.24 / Chapter 3.6. --- Reference --- p.25 / Chapter 4. --- Receiver Design --- p.26 / Chapter 4.1. --- Introduction --- p.26 / Chapter 4.2. --- Conventional Latched-typed Sense Amplifier --- p.27 / Chapter 4.3. --- Sense Amplifier with Isolated Differential Pair --- p.29 / Chapter 4.4. --- "Power Consumption, Latency and Kick-back Noise Comparison between Different Designs" --- p.30 / Chapter 4.4.1. --- Comparison on Power Consumption --- p.30 / Chapter 4.4.2. --- Comparison on Latency --- p.31 / Chapter 4.4.3. --- Comparison on Kick-back Noise --- p.33 / Chapter 4.5. --- Summary --- p.34 / Chapter 4.6. --- Reference --- p.34 / Chapter 5. --- Inverter Chain --- p.36 / Chapter 5.1. --- Introduction --- p.36 / Chapter 5.2. --- Inverter Chain Based --- p.36 / Chapter 5.3. --- Summary --- p.38 / Chapter 5.4. --- References --- p.38 / Chapter 6. --- Layout Techniques --- p.39 / Chapter 6.1. --- Introduction --- p.39 / Chapter 6.2. --- Two-Dimensional Common Centroid Layout Technique --- p.39 / Chapter 6.3. --- Dummy Devices --- p.40 / Chapter 6.4. --- Summary --- p.42 / Chapter 6.5. --- References --- p.42 / Chapter 7. --- Simulation Results --- p.43 / Chapter 7.1. --- Introduction --- p.43 / Chapter 7.2. --- Simulation of Different Aspect Ratios of Differential Pair --- p.43 / Chapter 7.3. --- System Level Simulation with Different Sense-amplifiers --- p.46 / Chapter 7.4. --- System Level Simulation at Different Data Rate --- p.47 / Chapter 7.5. --- Summary --- p.49 / Chapter 8. --- Measurement Results --- p.50 / Chapter 8.1. --- Introduction --- p.50 / Chapter 8.2. --- Experimental Setup --- p.50 / Chapter 8.2.1. --- Testing Chips --- p.50 / Chapter 8.2.2. --- Equipments Setup --- p.52 / Chapter 8.3. --- Measurement Results --- p.53 / Chapter 8.4. --- Summary --- p.56 / Chapter 9. --- Conclusion --- p.57 / Chapter 9.1. --- Author´ةs Contributions --- p.57 / Chapter 9.2. --- Future Works --- p.58 / Chapter 10. --- Appendix --- p.59

Leung, Chi Kwan. / Thesis submitted in: December 2007. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 66-68). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Literature Review on Fixed-outline Floorplanning --- p.5 / Chapter 2.1 --- General Floorplanning --- p.5 / Chapter 2.1.1 --- Simulated Annealing --- p.6 / Example - Normalized Polish Expression --- p.9 / Example - Sequence Pair Representation --- p.15 / Example - Corner Block List --- p.19 / Chapter 2.1.2 --- Genetic Algorithm --- p.24 / Chapter 2.1.3 --- Mixed Integer Linear Programming --- p.25 / Chapter 2.1.4 --- Geometric Programming --- p.25 / Chapter 2.1.5 --- Discussion --- p.26 / Advantages of using Simulated Annealing --- p.26 / Disadvantages of using Simulated Annealing --- p.27 / Chapter 2.2 --- Fixed-outline Floorplanning --- p.28 / Chapter 2.2.1 --- Motivation --- p.28 / Chapter 2.2.2 --- Dimension Based Cost Function --- p.30 / Chapter 2.2.3 --- Aspect Ratio Based Cost Function --- p.32 / Chapter 2.2.4 --- Evolutionary Search --- p.33 / Chapter 2.2.5 --- Instance Augmentation --- p.35 / Chapter 3 --- Predictive Rating with Fixed Outline Constraints --- p.39 / Chapter 3.1 --- Introduction --- p.39 / Chapter 3.2 --- Motivation --- p.40 / Chapter 3.3 --- Predictive Rating Scheme --- p.44 / Chapter 3.3.1 --- Area --- p.45 / Chapter 3.3.2 --- Dimensions --- p.46 / Chapter 3.3.3 --- Aspect Ratio --- p.47 / Chapter 3.3.4 --- Overall Equation for Predictive Rating --- p.48 / Chapter 3.4 --- Integration into the Floorplanner --- p.49 / Chapter 3.5 --- Experimental Results --- p.50 / Chapter 3.5.1 --- Accuracy of Predictive Rating --- p.50 / Chapter 3.5.2 --- Test One --- p.52 / Chapter 3.5.3 --- Test Two --- p.57 / Chapter 3.6 --- Conclusion --- p.61 / Chapter 4 --- Conclusion --- p.64 / Bibliography --- p.66

Jiang, Yan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (p. 87-92). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Physical Design --- p.2 / Chapter 1.2 --- Floorplanning --- p.6 / Chapter 1.2.1 --- Floorplanning Objectives --- p.7 / Chapter 1.2.2 --- Common Approaches --- p.8 / Chapter 1.3 --- Motivations and Contributions --- p.14 / Chapter 1.4 --- Organization of the Thesis --- p.15 / Chapter 2 --- Literature Review on BDF --- p.17 / Chapter 2.1 --- Zero-Bend BDF --- p.17 / Chapter 2.1.1 --- BDF Using the Sequence-Pair Representation --- p.17 / Chapter 2.1.2 --- Using B*-Tree and Fast SA --- p.20 / Chapter 2.2 --- Two-Bend BDF --- p.22 / Chapter 2.3 --- TCG-Based Multi-Bend BDF --- p.25 / Chapter 2.3.1 --- Placement Constraints for Bus --- p.26 / Chapter 2.3.2 --- Bus Ordering --- p.28 / Chapter 2.4 --- Bus-Pin-Aware BDF --- p.30 / Chapter 2.5 --- Summary --- p.33 / Chapter 3 --- Fixed-Outline BDF --- p.35 / Chapter 3.1 --- Introduction --- p.35 / Chapter 3.2 --- Problem Formulation --- p.36 / Chapter 3.3 --- The Overview of Our Approach --- p.36 / Chapter 3.4 --- Partitioning --- p.37 / Chapter 3.4.1. --- The Overview of Partitioning --- p.38 / Chapter 3.4.2 --- Building a Hypergraph G --- p.39 / Chapter 3.5 --- Floorplaiining with Bus Routing --- p.43 / Chapter 3.5.1 --- Find Bus Routes --- p.43 / Chapter 3.5.2 --- Realization of Bus Routes --- p.48 / Chapter 3.5.3 --- Details of the Annealing Process --- p.50 / Chapter 3.6 --- Handle Fixed-Outline Constraints --- p.52 / Chapter 3.7 --- Bus Layout --- p.52 / Chapter 3.8 --- Experimental Results --- p.56 / Chapter 3.9 --- Summary --- p.61 / Chapter 4 --- Fixed-Outline BDF with L-shape bus --- p.63 / Chapter 4.1 --- Introduction --- p.63 / Chapter 4.2 --- Problem Formulation --- p.64 / Chapter 4.3 --- Our Approach --- p.65 / Chapter 4.3.1 --- Bus Routability Checking --- p.67 / Chapter 4.3.2 --- Details of the Annealing Process --- p.79 / Chapter 4.4 --- Experimental Results --- p.79 / Chapter 4.5 --- Summary --- p.82 / Chapter 5 --- Conclusion --- p.85 / Bibliography --- p.92

One-dimensional (1D) nanomaterial self-assembly offers an excellent approach to the fabrication of highly complex nanodevices. Despite considerable effort and research, precisely controlling the orientation and positioning of nanowires (NWs) on a large-scale area and assembling into a functional device is still a state of the art problem. This thesis focuses on the dimensionally controlled copper nanowires (Cu NWs) synthesis, and magnetic field assisted self-assembly of cupronickel nanowires (Cu/Ni NWs) into interconnect structures on a carbon doped silicon dioxide (CDO) wafer. CDO is a low dielectric constant (k) material used for copper interconnects in multilayered complex integrated circuits (ICs). Here, a strong affinity of copper (Cu) and nickel (Ni) to thiol (-SH) functional groups were exploited to strongly adhere the nanowires (Cu/Ni NWs) onto the CDO substrate. Thiol (-SH) functionalization of the CDO surface was achieved via a series of reactions involving (1) esterification of the surface exposed ≡Si-OH functional group to its triflate (≡Si-O-Tf), (2) reduction of triflate to ≡Si-H using DIBAL-H, and (3) hydrosilylation of ≡Si-H using 2-propene thiol (≡Si-(CH2)3-SH) in a photochemical reaction. The thiol functionalization of CDO surface enhances the interaction of Cu/Ni NWs with strong chemical bonds. The same reaction scheme was also used in the functionalization of the hydrophilic (Si-OH) surface to the hydrophobic long alkyl chain derivatized (≡Si-CH2-(CH2)16-CH3) surface. This long alkyl chain modified surface acts as an excellent moisture resistant film, which helps to maintain the low-k value of CDO. The dimensionally controlled Cu NWs were synthesized by a wet chemical approach. Optimization of the reducing agent, hydrazine (N2H4), controlled the surface morphology of nanowires (NWs). Interestingly, the high concentration of reducing agent produced particle decorated and/or with a rough NW surface, and conversely decreasing its concentration resulted in a comparatively thin, particle-free and smooth surface. The reaction temperature affected the aspect ratio (Length/Diameter) of the NWs. As the reaction temperature increased from 60 to 90 °C, the aspect ratio decreased from 140 to 21. Controlling the orientation of Cu NWs in a magnetic field was accomplished by coating them with a thin layer (~20 nm) of ferromagnetic nickel (Ni). This Ni-coated NWs showed an excellent degree of alignment (half-width ≈10 degrees) in the direction of an applied magnetic field over a large surface area at field strength as low as 2500 Gauss. Also, the Ni coating helped in protecting the copper core from oxidation resulting in better electrical wire-to-wire contacts. A nanowire-based interconnect channel was fabricated by combining magnetic field assisted alignment and deposition of aligned NWs on a thiol-modified and photolithography patterned CDO substrate. The NWs, deposited in the trenches, strongly bonded to the thiol-derivatized CDO substrate while an acetone wash removed loosely bound NWs on the photoresist surface. In electrical characterization, the directionally well-aligned Cu/Ni NWs channel displayed surprisingly two-fold higher conductivity than randomly arranged NWs channel.

The potential failure in through-silicon vias (TSVs) still poses a challenge in trying to extend the useful life of a 3D integrated circuit (IC). A model is proposed to mitigate the communication problem in 3D integrated circuits caused by the breaks at the TSVs. We provide the details of a low-complexity network that takes advantages of redundant TSVs to make it possible to re-route around breaks and maintain effective communication between layers. Different configurations for the micronetwork are analyzed and discussed. We also present an evaluation of the micronetwork's performance, which turns out to be quite promising, based on several Monte Carlo simulations. Finally, we provide some directions for future research on the subject.

"More Than Moore's Law" is the driving principle for the electronic packaging industry. This principle focuses on system integration instead of transistor density in order to achieve faster, thinner, and smarter electronic devices at a low cost. A core area of electronics packaging is interconnection technology, which enables ultra-miniaturization and high functional density. Solder bump technology is one of the original, and most common interconnection methods for flip chips. With growing demand for finer pitch and higher number of I/Os, solder bumps have been forced to smaller dimensions and therefore, are subjected to higher current densities. However, the technology is now reaching its fundamental limitations in terms of pitch, processability, and current-handling due to electromigration. Electromigration in solder bumps is one of the major causes of device failures. It is accelerated by many factors, one of which is current crowding. Current crowding is the non-uniform distribution of current at the interface of the solder bump and under-bump metallurgy, resulting in an increase in local current density and temperature. These factors, along with the formation of intermetallic compounds, can lead to voiding and ultimately failure. Electromigration in solder bumps has prevented pitch-scaling below 180-210 microns, producing a shift in the packaging industry to other interconnection approaches, specifically copper pillars with solder. This research aims to explore the electromigration resistance of an adhesive-based copper-to-copper (Cu-Cu) interconnection method without solder, which is thermo-compression bonded at a low temperature of 180C. While solder bumps are more susceptible to electromigration, Cu is capable of handling two orders of magnitude higher current density. This makes it an ideal candidate for next generation flip chip interconnections. Using finite element analysis, the current crowding and joule heating effects were evaluated for a 30 micron diameter Cu-Cu interconnection in comparison with two existing flip chip interconnection techniques, Cu pillar with solder and Pb-free solder. A test vehicle (TV) was fabricated for experimental analysis with 760 bumps arranged in an area-array format with a bump diameter of 30 micron. Thermo-mechanical reliability of the test vehicle was validated under thermal cycling from -55C to 125C. The Cu-Cu interconnections were then subjected to high current and temperature stress from 1E4 to 1E6 amps per square centimeter at a temperature of 130C. The results establish the high thermo-mechanical reliability and high electromigration resistance of the proposed Cu-Cu interconnection technology.

Imaging of current in internal conductors through magnetic field detection by magnetic force microscopy (MFM) is of growing interest in the analysis of integrated circuits (ICs). This thesis presents a systematic study of the MFM based mapping of current in model circuits by using force and force gradient techniques. In comparing these two techniques, force was found to have a much higher signal to noise ratio (from ~150 to ~580 times) than force gradient at large tip-sample distances considering the presence of thick overlayers in ICs. As a result, force will have better sensitivity and can therefore be used to detect much smaller minimum currents. We have achieved a sensitivity of ~0.64 µA per square-root Hertz in air and ~0.095 µA per squre-root Hertz in vacuum for force with a pinning field with a probe-circuit separation of 1.0 µm. We conclude that the force technique is superior for the application of MFM current imaging of buried conductors, albeit with reduced spatial resolution. Numerical modeling of the MFM images has shown that the simple point probe approximation is insufficient to model MFM images. An extended model, which considers realistic MFM probe geometries and the forces acting on the whole probe, has been shown to be necessary. Qualitative and quantitative comparisons of the experimental and simulation results with this model are in agreement to within experimental uncertainty. The comparisons suggested that the CoCr film thickness is not uniform on the probe, which was verified by scanning electron microscope cross-section images of the probes cut by a focused ion beam. Most notably, the CoCr film was 1.5 times thicker on the cantilever than on the tip. Based on the simulation and experimental results, we have devised a method to accurately locate the current path from MFM images with submicrometer uncertainty. The method was tested for different patterns of model conducting lines. It was shown to be a useful technique for fault location in IC failure analysis when current flows through the devices buried under overlayers and no topographic features are on the surface to provide clues about the positions of the devices. / October 2007

The interconnect fabric that provides electrical connectivity to active devices is an essential component to modern semiconductor chips. As the dimensions of these devices are scaled to improve performance and keep pace with Moore's Law, the local Cu interconnects must scale in parallel. Intrinsic material properties of Cu result in spiking electrical resistivity with scaling and present a looming bottleneck to chip performance. In this thesis, we introduce graphene as a replacement material to Cu interconnects in support of future chip scaling. In particular we focus on experimentally establishing fundamental mechanisms of chemically doping graphene via the basal plane and edge passivation, with broad contributions that extend beyond the focus of local interconnects.