published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

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The microelectronics industry has been managing the RC delay problem arising from aggressive line scaling, by replacing aluminum (Al) by copper (Cu) and oxide dielectric by low-k dielectric. Electromigration (EM) turned out to be a serious reliability problem for Cu interconnects due to the implementation of mechanically weaker low-k dielectrics. In addition, line width and via size scaling resulted in the need of a novel diffusion barrier, which should be uniform and thin. The objective of this dissertation is to investigate the impacts of Ta barrier process, such as barrier-first and pre-clean first, and scaling of barrier and line/via on EM reliability of Cu/low-k interconnects. For this purpose, EM statistical test structures, having different number of line segments, line width, and via width, were designed. The EM test structures were fabricated by a dualdamascene process with two metal layers (M1/Via/M2), which were then packaged for EM tests. The package-level EM tests were performed in a specially designed vacuum chamber with pure nitrogen environment. The novel barrier deposition process, called barrier-first, showed a higher (jL)[subscript c] product and prolonged EM lifetime, compared with the conventional Ta barrier deposition process, known as pre-clean first. This can be attributed to the improved uniformity and thickness of the Ta layer on the via and trench, as confirmed by TEM. As for the barrier thickness effect, the (jL)c product decreased with decreasing thickness, due to reduced Cu confinement. A direct correlation between via size and EM reliability was found; namely, EM lifetime and statistics degraded with via size. This can be attributed to the fact that critical void length to cause open circuit is about the size of via width. To investigate further line scaling effect on EM reliability, SiON (siliconoxynitride) trenchfilling process was introduced to fabricate 60-nm lines, corresponding to 45-nm technology, using a conventional, wider line lithograph technology. The EM lifetime of 60-nm fine lines with SiON filling was longer than that of a standard damascene structure, which can be attributed to a distinct via/metal-1 configuration in reducing process-induced defects at the via/metal-1 interface. / text

In the modern world of technology, highly sophisticated electronic systems pave the way for future's information technology breakthroughs. However, rapid growth on complexity and functions in such systems has also been a harbinger for the power increase. Power management techniques have thus been introduced to mitigate this urgent power crisis. Switching power converters are considered to be the best candidate due to their high efficiency and voltage conversion flexibility. Moreover, switching power converter systems are highly nonlinear, discontinuous in time, and variable. This makes it viable over a wide operating range, under various load and line disturbances. However, only one control scheme cannot optimize the whole system in different scenarios. Hybrid control schemes are thus employed in the power converters to operate jointly and seamlessly for performance optimization during start-up, steady state and dynamic voltage/load transient state.In this dissertation, three switching power converter topologies, along with different hybrid control schemes are studied. First, an integrated switching buck converter with a dual-mode control scheme is proposed. A pulse-train (PT) control, employing a combination of four pulse control patterns, is proposed to achieve optimal regulation performance. Meanwhile, a high-frequency pulse-width modulation (PWM) control is adopted to ensure low output ripples and avoid digital limit cycling. Second, an integrated buck-boost converter with a tri-mode digital control is presented. It employs adaptive step-up/down voltage conversion to enable a wide range of output voltage. This is beneficial to ever-increasing dynamic voltage scaling (DVS) enabled, modern power-efficient VLSI systems. DVS adaptively adjusts the supply voltage and operation frequency according to instantaneous power and performance demand, such that a system is constantly operated at the lowest possible power level without compromising its performance. Third, a digital integrated single-inductor multiple-output (SIMO) converter, tailored for DVS-enabled multicore systems is addressed. With a multi-mode control algorithm, DVS tracking speed and line/load regulation are significantly improved, while the converter still retains low cross regulation.All three integrated CMOS DC-DC converters have been designed and fabricated successfully, demonstrating the techniques proposed in this research. The measurements results illustrate superior line and load regulation performances and dynamic response in all these designs.

Microwave circuit design including the design of Interconnect circuits are proving to be a very hard and complex process where the use of CAD tools is becoming more essential to the reduction in design time and in providing more accurate results. Space mapping methods, the relatively new and very efficient way of optimization which are used in microwave filters and structures will be investigated in this thesis and applied to the time domain optimization of digital interconnects. The main advantage is that the optimization is driven using simpler models called coarse models that would approximate the more complex fine model of the real system, which provide a better insight to the problem and at the same time reduce the optimization time. The results are always mapped back to the real system and a relation/mapping is found between both systems which would help the convergence time. In this thesis, we study the optimization of interconnects where we build certain practical error functions to evaluate performance in the time domain. The space mapping method is formulated to avoid problems found in the original formulation where we apply some necessary modifications to the Trust Region Aggressive Space Mapping TRASM for it to be applicable to the design process in time domain. This new method modified TRASM or MTRASM is then evaluated and tested on multiple circuits with different configuration and the results are compared to the results obtained from TRASM.

This thesis examines the design of high speed transimpedance amplifiers (TIAs) in low cost complimentary metal oxide semiconductor (CMOS) technology. Due to aggressive scaling, CMOS has become an attractive technology for high speed analog circuits. Besides the cost advantage, CMOS offers the potential for higher levels of integration since the analog circuits can be integrated with digital electronics on the same substrate. A 2.5 Gbps transimpedance amplifier fabricated using 0.18 um CMOS technology is presented. The TIA uses a shunt-shunt feedback topology with a cascode gain stage. Measurements of the transimpedance gain, group delay, and common mode rejection ratio are presented for the TIA and show a good match to simulated results. The noise of the TIA was characterized by measuring the noise parameters of the TIA. The noise parameters are then used to determine the input referred noise current spectral density. A 10 Gbps transimpedance amplifier fabricated using 0.18 um CMOS technology is also presented. This TIA uses a shunt-shunt feedback topology with a common source gain stage. In order to achieve the required bandwidth, the TIA uses a bandwidth extension technique called shunt-series inductive peaking. A discussion of the different methods of bandwidth extension using inductive peaking is included, and the optimal configurations for maximally flat responses are shown for shunt inductive peaking,series inductive peaking, and shunt-series inductive peaking. The TIA circuit topology is optimized using a novel noise analysis that uses a high frequency noise model for the transistor. The optimum transistor size and bias current are determined to minimize the amplifier noise. Unfortunately differential measured results are not available due to a stability problem in the amplifier. The cause of this instability is further explored and modifications to solve the problem are discussed. Single-ended results are presented and show reasonable agreement with simulated results. Differences in the results are attributed to poor modelling of the on-chip spiral inductors. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-07-16 13:34:41.46

This thesis presents the design and analysis of two high speed analog laser driver stages (LDS) for use in a passive optical network (PON) upstream burst-mode transmitter (BM-Tx) using low cost complementary metal oxide semiconductors (CMOS) technology. The maturation of CMOS technology has lead to aggressive scaling of device sizes which has made it an increasingly attractive technology for high speed analog design. CMOS provides high levels of integration as it is the industry standard for digital circuits, analog and digital systems can share one substrate reducing costs. Additionally CMOS is a more cost effective solution than traditional expensive high speed analog substrates. A 2.5 Gbps LDS fabricated in 0.18 um CMOS technology is presented. The LDS uses a two stage per-amplifier. Stage one consists of a cascode differential pair with a source follower voltage buffer, while stage two consists of a shunt inductively peaked differential pair using active inductors. A differential pair composed of large transistors is used in an open drain configuration for the output stage. Measurements of S-parameters are presented which accurately agree with simulations. Electrical eye diagram measurements are presented which demonstrate the LDS is able to provide a modulation current of 14.6-58 mA. 10%-90% approximate rise/fall times of 230/260 ps was obtained for a modulation current of 58 mA. Power consumption of the core was determined to be 68.5 mW, while the chip consumed an area of 0.8 mm x 0.7 mm including pads. A 10 Gbps LDS fabricated in 0.18 um CMOS technology is also presented. The LDS uses a cascode differential pair for the output stage. The per-amplifier for this design consists of a differential pair and utilizes spiral inductors for series inductive peaking between the per-amplifier and output stage. Measurements of S-parameters are presented which accurately agree with simulations. Electrical eye diagram measurements are presented which demonstrate the LDS is able to provide a modulation current of 22.6-62 mA. 10%-90% rise/fall time of 87 ps and 75 ps are respectively obtained while operating at maximum modulation current. The core of the LDS consumes a power of 287 mW, while the chip consumed an area of 0.79 mm x 0.7mm. The measured electrical eye diagrams for the 2.5 Gbps and the 10 Gbps meet the timing requirements for the GPON standard. Further work is needed to investigate whether or not the timing requirements would still be met once the CMOS chips are integrated with commercial laser diodes. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2010-09-24 10:43:33.418

Imaging of current in internal conductors through magnetic field detection by magnetic force microscopy (MFM) is of growing interest in the analysis of integrated circuits (ICs). This thesis presents a systematic study of the MFM based mapping of current in model circuits by using force and force gradient techniques. In comparing these two techniques, force was found to have a much higher signal to noise ratio (from ~150 to ~580 times) than force gradient at large tip-sample distances considering the presence of thick overlayers in ICs. As a result, force will have better sensitivity and can therefore be used to detect much smaller minimum currents. We have achieved a sensitivity of ~0.64 µA per square-root Hertz in air and ~0.095 µA per squre-root Hertz in vacuum for force with a pinning field with a probe-circuit separation of 1.0 µm. We conclude that the force technique is superior for the application of MFM current imaging of buried conductors, albeit with reduced spatial resolution. Numerical modeling of the MFM images has shown that the simple point probe approximation is insufficient to model MFM images. An extended model, which considers realistic MFM probe geometries and the forces acting on the whole probe, has been shown to be necessary. Qualitative and quantitative comparisons of the experimental and simulation results with this model are in agreement to within experimental uncertainty. The comparisons suggested that the CoCr film thickness is not uniform on the probe, which was verified by scanning electron microscope cross-section images of the probes cut by a focused ion beam. Most notably, the CoCr film was 1.5 times thicker on the cantilever than on the tip. Based on the simulation and experimental results, we have devised a method to accurately locate the current path from MFM images with submicrometer uncertainty. The method was tested for different patterns of model conducting lines. It was shown to be a useful technique for fault location in IC failure analysis when current flows through the devices buried under overlayers and no topographic features are on the surface to provide clues about the positions of the devices.

Emerging I/O density and bandwidth requirements are driving packages to low-CTE silicon, glass and organic substrates for higher wiring density and reliability of interconnections and Cu-low k dielectrics. These are needed for high performance applications as 2.5D packages in large-size, and also as ultra-thin packages for consumer applications that are directly assembled on the board without the need for an intermediate package. The trend to low-CTE packages (CTE of 3-8ppm/°C), however, creates large CTE mismatch with the board on which they are assembled. Interconnection reliability is, therefore, a major concern when low CTE interposers are surface mounted onto organic system boards via solder joints. This reliability concern is further aggravated with large package sizes and finer pitch. For wide acceptance of low CTE packages in high volume production, it is also critical to assemble them on board using standard Surface Mount Technologies (SMT) without the need for under-fill. This research aims to demonstrate reliable 400 micron pitch solder interconnections from low CTE glass interposers directly assembled onto organic boards by overcoming the above challenges using two approaches; 1) Stress-relief dielectric build up layers on the back of the interposer, 2) Polymer collar around the solder bumps for shear stress re-distribution. A comprehensive methodology based on modeling, design, test vehicle fabrication and characterization is employed to study and demonstrate the efficacy of these approaches in meeting the interposer-to-board interconnection requirements. The effect of varying geometrical and material properties of both build-up layers and polymer collar is studied through Finite Element Modeling. Interposers were designed and fabricated with the proposed approaches to demonstrate process feasibility.

The main objective of this dissertation is to investigate a design methodology that can characterize and compensate for process and temperature variation. First, a design methodology is discussed to handle process variation in low-power memory for image processing application. This is followed by a design technique to characterize and recover TSV-defect-induced signal degradation in a 3D integrated circuit. For thermal variation, the spatiotemporal power migration is proposed as a methodology to handle thermal issues in digital systems both during the test and normal operation. The power migration continuously distributes the generated heat in space and time to control chip temperature. To enable this approach a unique method is developed, and verified through hardware for post-fabrication characterization of thermal system and prediction of transient variation in chip temperature. The inverse temperature dependence in a digital logic is characterized through hardware to help better thermal management in wide operating voltage design.