A molecular dynamics coarse-grained block copolymer (BCP) model was developed and used to studied directed self-assembly (DSA), especially in regards to applications for semiconductor manufacturing. Most of the thesis is spent investigating the effect that guiding layer properties and block copolymer properties have on line roughness and defect density in a BCP-DSA process. These two effects are perhaps the most critical in making BCP-DSA a cost efficient industrial process. It is found that guiding patterns have little effect on line roughness and in fact that the BCP heals the majority of roughness in the underlying pattern. BCP properties have a larger effect on line roughness. Segregation strength (as measured by χN, where χ is the Flory- Huggins interaction parameter and N is the degree of polymerization) resulted in a larger than expected increase in line roughness when χN was low. Polydispersity resulted in a moderate increase in line roughness. In regards to equilibrium defect density, free energy calculations showed that χ was the primary determining factor, not χN as many expected. Equilibrium defect density was found to decrease exponentially with increasing χ. Defect density is also found to scale exponentially with polydispersity. Concerning defect heal rate, which can increase the real defect rate of a process if said rate is too low, it is found that increasing χN linearly increased the barrier to defect healing, which means that the defect heal rate decreases exponentially. However, for thin films this is only true for χN > ~ 50. Below χN ~ 50, the barrier is approximately constant. These results give excellent guidance to the type of materials and processes necessary to optimize a BCP-DSA process. A simulation technique designed to more efficiently sample over energy barriers called protracted noise dynamics for polymer systems was developed and studied. It was found that a decrease in simulation time of up to 4 orders of magnitude was achieved. The effect of box size on allowable pitches for a lamellar forming BCP was derived and demonstrated. It was found that more elongated boxes yielded more possible pitches and more accurate results. A short study on the effect of multiblock copolymers on the location of the order-disorder transition was also carried out and it was found that multiblock copolymers had small effect on the ODT. The distribution of chain conformations was also calculated.

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

Phased array radar systems employ multiple antennas to create a radar beam that can be steered electronically. By manipulating the relative phase values of feeding signals among different antennas, the effective radiation pattern of the array can be synthesized to enhance the main lobe in a desired direction while suppressing the undesired side lobes in other directions. Hence the radar scanning angles can be electronically controlled without employing the bulky mechanical gimbal structure, which can significantly reduce radar system size, weight and power consumption. In recent years, phased array technologies have received great attentions and are explored in developing many new applications, such as smart communication systems, military radars, vehicular radar, etc. Most of these systems are narrow band systems, where the phase delays are realized with narrow band phase shifter circuits. For the impulse ground penetrating radar however, its operating frequency spans an ultrawide bandwidth. Therefore the traditional phase shifters are not applicable due to their narrow band nature. To resolve the issue, in this study, a true time delay approach is explored which can precisely control time delays for the feeding pulse signals among different antennas in the array. In the design, an on chip programmable delay generator is being developed using Global Foundry 0.18 µm 7 HV high voltage CMOS process. The time delay control is realized by designing a programmable phase locked loop (PLL) circuit which can generate true time delays ranging from 100 ps (picoseconds) to 500 ps with the step size of 25 ps. The PLL oscillator's frequency is programmable from 100MHz to 500MHz through two reconfigurable frequency dividers in the feedback loop. As a result, the antenna beam angle can be synthesized to change from 9.59° to 56.4° with a step of 2.75°, and the 3dB beamwidth is 10°. The power consumption of the time delay circuit is very low, where the supply voltage is 1.8V and the average current is as low as 472uA.

Selon l’ITRS, le transistor à nanotube de carbone est une des alternatives prometteuses au transistor MOS Silicium notamment en termes de taille de composant et d’architectures de circuits innovantes. Cependant, à l’heure actuelle, la maturité des procédés de fabrication de ces technologies ne permet pas de contrôler finement les caractéristiques électriques. C’est pourquoi, nous proposons un modèle compact basé sur les principes physiques qui gouvernent le fonctionnement du transistor à nanotube. Cette modélisation permet de lier les activités technologiques à celles de conception de circuit dans le contexte de prototypage virtuel. Pour peu qu’elle inclut des paramètres reflétant la variation des procédés, il est alors possible d’estimer les performances potentielles des circuits intégrés. Le transistor à nanotube de carbone à modulation de hauteur de barrière (C-CNFET), i.e. « MOS-like », est modélisé analytiquement en supposant le transport balistique des porteurs dans le canal. Le formalisme de Landauer est utilisé pour décrire le courant modulé par le potentiel du canal calculé de façon auto-cohérente avec la charge associée selon le potentiel appliqué sur la grille. Le modèle du transistor à nanotube de carbone double grille, DG-CNFET est basé sur celui du C-CNFET. Ce transistor est de type N ou P selon la polarisation de la grille supplémentaire. Ce transistor est modélisé de manière similaire pour les 3 régions : la partie interne modulée par la grille centrale, et les accès source et drain modulés par la grille arrière. La charge, plus complexe à calculer que celle du C-CNFET, est résolue analytiquement en considérant différentes plages de polarisation et d’énergie. Le modèle du DG-CNFET a été mis en œuvre dans le cadre d’architectures de circuits électroniques innovants : une porte logique à 2 entrées comportant 7 transistors CNFET dont 3 DG-CNFET pouvant, selon la polarisation des 3 entrées de configuration, réaliser 8 fonctions logiques différentes. / According to ITRS, the carbon nanotube transistor is one promising alternative to the silicon MOS transistor particularly in terms of device dimensions and novel circuit architectures. However, today, the fabrication processes maturity of these technologies does not allow controlling accurately their electrical characteristics. That’s why we propose a compact model based on physical principles that govern the nanotube transistor operation. That modelling allows linking the technological activities to the circuit design ones in the virtual prototyping context. As it includes parameters that reflect the processes variation, it is possible to estimate the potential performances of integrated circuits. The barrier-height modulated carbon nanotube transistor (C-CNFET), i.e. MOS-like transistor, is analytically modelled assuming ballistic transport of carriers in the channel. The Landauer’s formalism is used to describe the current modulated by the channel potential which is self-consistently calculated with the associated charge according to the gate potential. The model of the double-gate carbon nanotube transistor, DG-CNFET, is based on the C-CNFET one. That transistor is N or P type depending on the additional gate polarisation. That transistor is modelled in a similar way for the 3 regions: the inner part modulated by the central gate, and the source and drain accesses modulated by the back gate. The charge, more complex to calculate than the C-CNFET one, is analytically solved considering different polarisation and energy ranges. Moreover, the DG-CNFET model has been used into novel electronic circuit architectures: a 2 inputs logic gate, composed of 7 CNFET transistors, 3 of which are DG-CNFET, able to realize 8 different logic functions, according to the polarisation of the 3 configuration inputs.

Master of Science / Department of Electrical Engineering / William Kuhn / When enough charges accumulate on two objects, the air dielectric between them breaks down to create a phenomenon known as electrostatic discharge (ESD). ESD is of great concern in the integrated circuit industry because of the damage it can cause to ICs. The problem will only become worse as process components become smaller. The three main types of ESD experienced by an IC are the human body model (HBM), the charged device model (CDM), and the machine model (MM). HBM ESD has the highest voltage while CDM ESD has the highest bandwidth and current of the three ESD types. Integrated circuits generally include ESD protection circuitry connected to their pads. Pads are the connection between the IC and the outside world, making them the required location for circuitry designed to route ESD events away from the IC's internal circuitry. The most basic protection pads use diodes connected from I/O to VDD and I/O to ground. A voltage clamp between VDD and ground is also necessary to protect against CDM and MM event types where the device may not yet have a low impedance supply path connected. The purpose of this research is to investigate the performance of ESD circuits and to develop a method for detecting the occurrence of an ESD event in an integrated circuit by utilizing IC fuses. The combination of IC fuses and detection circuitry designed to sense a broken fuse allows the IC to perform a built-in self-test (BIST) for ESD to identify compromised ICs, preventing manufacturers from shipping damaged circuits. Simulations are used to design an optimized protection circuit to complement the proposed ESD detection circuit. Optimization of an ESD pad circuit increases the turn-on speed of its voltage clamps and decreases the series resistance of its protection diodes. These improvements minimize the stress voltage placed on internal circuitry due to an ESD event. An ESD measurement setup is established and used to verify voltage clamp operation. This research also proposes an ESD detection circuit based on IC fuses, which fail during an ESD event. A variety of IC fuses are tested using the ESD measurement setup as well as a TLP setup in order to determine the time and current needed for them to break. Suitable IC fuses have a resistance less than 5 Ω and consistently break during the first trial.

Today’s microprocessors with millions of transistors perform high-complexity computing at multi-gigahertz clock frequencies. The ever-increasing chip size and speed call for new methodologies in clock distribution network. Conventional global synchronization techniques exhibit many drawbacks in the advanced VLSI chips such as high-speed microprocessors. A significant percentage of the total power consumption in a microprocessor is dissipated in the clock distribution network. Also since the chip dimensions increase, clock skew management becomes very challenging in the framework of conventional methodology. Long interconnect delays limit the maximum clock frequency and become a bottleneck for future microprocessor design. In such a situation, new alternative techniques for synchronization in system-on-chip are demanded. This thesis presents new alternatives for traditional clocking and synchronization methods, in which, speed and power consumption bottlenecks are treated. For this purpose, two new techniques based on mesochronous synchronization and resonant clocking are investigated. The mesochronous synchronization technique deals with remedies for skew and delay management. Using this technique, clock frequency up to 5 GHz for on-chip communication is achievable in 0.18-μm CMOS process. On the other hand the resonant clocking solves significant power dissipation problem in the clock network. This method shows a great potential in power saving in very large-scale integrated circuits. According to measurements, 2.3X power saving in clock distribution network is achieved in 130-nm CMOS process. In the resonant clocking, oscillator plays a crucial role as a clock generator. Therefore an investigation about oscillators and possible techniques for jitter and phase noise reduction in clock generators has been done in this research framework. For this purpose a study of injection locking phenomenon in ring oscillators is presented. This phenomenon can be used as a jitter suppression mechanism in the oscillators. Also a new implementation of the DLL-based clock generators using ring oscillators is presented in 130-nm CMOS process. The measurements show that this structure operates in the frequency range of 100 MHz-1.5 GHz, and consumes less power and area compared to the previously reported structures. Finally a new implementation of a 1.8-GHz quadrature oscillator with wide tuning range is presented. The quadrature oscillators potentially can be used as future clock generators where multi-phase clock is needed. / Report code: LiU-TEK-LIC-2006:22

Durant la dernière décennie, la miniaturisation des technologies de semi-conducteurs et de l’intégration à grande échelle a donné lieu à la conception de systèmes complexes, notamment l’intégration de plusieurs milliards de transistors sur un même die. Cette tendance pose de nombreux défis de fabrication et de fiabilité tels que la dissipation de puissance, la variabilité technologique et la polyvalence des applications. Les problèmes de fiabilité, représentées par la présence de points chauds thermiques peuvent accélérer la dégradation des transistors, et par conséquent réduire la durée de vie des puces, également appelée "vieillissement". Afin de relever ces défis, de nouvelles solutions sont nécessaires, basées notamment sur des systèmes auto-adaptatifs. Ces systèmes sont principalement composées d’une boucle de contrôle avec trois processus : (i) la surveillance, qui est chargée d’observer l’état du système, (ii) la prise de décision, qui analyse les informations collectées et prend des décisions pour optimiser le comportement du système et (iii) l’action qui ajuste les paramètres du système en conséquence. Cependant, une adaptation dépendre de façon critique sur le processus de suivi qui devrait fournir une estimation précise sur l’état du système de façon rentable. Dans cette thèse, nous étudions d’abord le suivi de la consommation d’énergie. Nous développons une méthode basée sur plusieurs algorithmes de fouille de données "data mining", pour surveiller l’activité de commutation sur quelques signaux pertinents sélectionnés au niveau RTL. La méthode proposée se compose d’un flot générique qui peut être utilisé pour modéliser la consommation d’énergie pour n’importe quel circuit RTL sur n’importe quelle technologie. Deuxièmement, nous améliorons le flot proposé pour estimer le comportement thermique globale de puce et de développer une nouvelle technique de placement des capteurs thermique sur puce. Les algorithmes proposés choisissent systématiquement le meilleur compromis entre la précision de l’observation et le coût représenté par le nombre de capteurs intégrés sur puce. La surface de la puce est décomposée en plusieurs zones thermiquement homogènes.Outre la partie conception, les systèmes embarqués modernes intègrent des capteurs matériels (analogiques ou numériques) qui peuvent être utilisés pour surveiller l’état du système. Ces méthodes industrielles sont généralement très coûteuses et nécessitent un grand nombre d’unités pour produire des informations précises avec une résolution à grain fin. Une solution alternative pour fournir une estimation précise de l’état du système est réalisée avec un ensemble de compteurs de performance qui peut être configuré pour effectuer le suivi des événements logiques à différents niveaux. Dans ce cas, nous proposons un nouvel algorithme pour la sélection des événements performance pertinents à partir des ressources locales, partagées et système. Nous proposons ensuite une implémentation d'un algorithme d'estimation basé sur un réseau neuronal. La méthode proposée est robuste contre les variations de température extérieure. En outre, estimation thermique est aussi peut être réalisé en utilisant les événements logiques actuelles et historiques, et la précision est évaluée sur la base de la profondeur dans le passé.Enfin, une fois la méthode de suivi et la cible définies et le système est configuré, la méthode de surveillance doit être utilisée au moment de "Run-time". Nous avons mis en place une boucle d’adaptation complète, avec un suivi dynamique de l’état du système afin atteindre une meilleure efficacité énergétique. / Over the last decade, the miniaturization of semiconductor technologies and the large-scale integration has given rise to complex system design, including the integration of several billions of transistors on a single die. This trend poses many manufacturing and reliability challenges such as power dissipation, technological variability and application versatility. The reliability issues represented by the presence of thermal hotspots can accelerate the degradation of the transistors, and consequently reduce the chip lifetime, also referred to as “aging”. In order to address these challenges, new solutions are required, based in particular on self-adaptive systems. Such systems are mainly composed of a control loop with three processes: (i) the monitoring, which is responsible for observing the state of the system, (ii) the diagnosis, which analyzes the information collected and makes decisions to optimize the behavior of the system, and (iii) the action that adjusts the system parameters accordingly. However, effective adaptations depend critically on the monitoring process that should provide an accurate estimation about the system state in a cost-effective manner. In this thesis, we firstly investigate the monitoring of the power consumption. We develop a method, based on several data mining algorithm, to monitor the toggling activity on a few relevant signals selected at the RTL level. The proposed method consists of a generic flow that can be used to model the power consumption for any RTL circuit on any technology. Secondly, we improve the proposed flow by estimating the overall chip thermal behavior and developing a new technique of on-die thermal sensor placement. The proposed algorithms systematically choose the best trade-off between accuracy and overhead. The surface of the chip is decomposed into several thermally homogeneous regions.Besides the design part, modern embedded systems integrates hardware sensors (analog or digital) that can be used to monitor the system’s state. These industrial methods are usually very expensive, and require a large number of units to produce precise information at a fine-grained resolution. An alternative solution to provide an accurate estimation of system’s state is achieved with a set of performance counters that can be configured to track logical events at different levels. To this end, we propose a novel algorithm for the selection of the relevant performance events from the local, shared and system resources. We propose then an implementation of a neural network based estimation algorithm. The proposed method is robust against the external temperature variations. Furthermore, thermal estimation is also can be achieved using the current and historic logical events, and the accuracy is evaluated on the basis of the depth in the past.Finally, once the tracking method and target are defined and the system is configured, the monitoring method should be used at “Run-time”. We implemented a complete adaptation loop, with a dynamic monitoring of the system’s state in order to achieve better energy efficiency.

De nos jours, le LASER reste l'outil le plus efficace et le plus utilisé pour injecter des fautes au sein des micro-contrôleurs sécurisés modernes. Parmi ses principaux avantages nous pouvons citer ses fortes résolutions spatiale et temporelle. Ces avantages ne sont toutefois accessibles qu'au prix d'investissements conséquents en temps et argent avec un coût oscillant entre deux et quatre centaines de milliers d'euros selon la qualité du LASER.Outre ces aspects financiers, la publication par les scientifiques, ainsi que l'intégration par les fabricants de cartes à puce, de contre-mesures efficaces, comme les détecteurs de lumière, ont incité aux développements de techniques d'injection de fautes alternatives et à coûts plus modérés. Parmi ces techniques alternatives, nous trouvons les techniques d'injection de faute(s) par médium électromagnétique qui permettent de perturber le comportement des circuits. C'est dans ce contexte que cette thèse présente les principaux effets de ce type d'injection de fautes en procédant à une première décomposition face avant face arrière, puis à une seconde lié à la forme du signal perturbateur utilisé (harmonique ou pulsé). Nous avons ainsi pu mettre en exergue des effets de coulage avec les lignes de métallisations mais aussi des effets de Forward sur le circuit cible. / Nowadays, LASER remains the tool the most effective and most used to inject faults within the modern secure microcontrollers. Among its main advantages we can quote its strong spatial and temporal resolutions. These advantages are however accessible only to the price of consequent investments in time and money with a cost oscillating between two and four hundreds of thousand euro according to the quality of the LASER. Besides these financial aspects, the publication by scientists, as well as the integration by the manufacturers of smart cards, effective countermeasures, as light detectors, incited to the development of alternative faults injection techniques with moderate costs. Among these alternative techniques, we find the electromagnetic fault injection techniques which allow perturbing the behavior of circuits. It is in this context that this thesis presents the main effects of this kind of fault injection by proceeding to a first decomposition in front side and back side, then in one second bound to the shape of the disturbing signal (harmonic or pulsed) used. So, we highlight coupling effects with metals lines but also a Forward effect on the target circuit.

Sham Chiu Wing. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 107-113). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Progress on the Problem --- p.2 / Chapter 1.3 --- Our Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.5 / Chapter 2 --- Preliminaries --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.1.1 --- The Role of Floorplanning --- p.6 / Chapter 2.1.2 --- Wirelength Estimation --- p.7 / Chapter 2.1.3 --- Different Types of Floorplan --- p.8 / Chapter 2.2 --- Representations of Floorplan --- p.10 / Chapter 2.2.1 --- Polish Expressions --- p.10 / Chapter 2.2.2 --- Sequence Pair --- p.11 / Chapter 2.2.3 --- Bounded-Sliceline Grid (BSG) Structure --- p.13 / Chapter 2.2.4 --- O-Tree --- p.14 / Chapter 2.2.5 --- B*-Tree --- p.16 / Chapter 2.2.6 --- Corner Block List --- p.18 / Chapter 2.2.7 --- Twin Binary Tree --- p.19 / Chapter 2.2.8 --- Comparisons between Different Representations --- p.20 / Chapter 2.3 --- Algorithms of Floorplan Design --- p.20 / Chapter 2.3.1 --- Constraint Based Floorplanning --- p.21 / Chapter 2.3.2 --- Integer Programming Based Floorplanning --- p.21 / Chapter 2.3.3 --- Neural Learning Based Floorplanning --- p.22 / Chapter 2.3.4 --- Rectangular Dualization --- p.22 / Chapter 2.3.5 --- Simulated Annealing --- p.23 / Chapter 2.3.6 --- Genetic Algorithm --- p.23 / Chapter 2.4 --- Summary --- p.24 / Chapter 3 --- Literature Review on Interconnect-Driven Floorplanning --- p.25 / Chapter 3.1 --- Introduction --- p.25 / Chapter 3.2 --- Simulated Annealing Approach --- p.25 / Chapter 3.2.1 --- """Pepper - A Timing Driven Early Floorplanner""" --- p.25 / Chapter 3.2.2 --- """A Timing Driven Block Placer Based on Sequence Pair Model""" --- p.26 / Chapter 3.2.3 --- """Integrated Floorplanning and Interconnect Planning""" --- p.27 / Chapter 3.2.4 --- """Interconnect Driven Floorplanning with Fast Global Wiring Planning and Optimization""" --- p.27 / Chapter 3.3 --- Genetic Algorithm Approach --- p.28 / Chapter 3.3.1 --- "“Timing Influenced General-cell Genetic Floorplanning""" --- p.28 / Chapter 3.4 --- Force Directed Approach --- p.29 / Chapter 3.4.1 --- """Timing Influenced Force Directed Floorplanning""" --- p.29 / Chapter 3.5 --- Congestion Planning --- p.30 / Chapter 3.5.1 --- """On the Behavior of Congestion Minimization During Placement""" --- p.30 / Chapter 3.5.2 --- """Congestion Minimization During Placement""" --- p.31 / Chapter 3.5.3 --- "“Estimating Routing Congestion Using Probabilistic Anal- ysis""" --- p.31 / Chapter 3.6 --- Buffer Planning --- p.32 / Chapter 3.6.1 --- """Buffer Block Planning for Interconnect Driven Floor- planning""" --- p.32 / Chapter 3.6.2 --- """Routability Driven Repeater Block Planning for Interconnect- centric Floorplanning""" --- p.33 / Chapter 3.6.3 --- """Provably Good Global Buffering Using an Available Block Plan""" --- p.34 / Chapter 3.6.4 --- "“Planning Buffer Locations by Network Flows""" --- p.34 / Chapter 3.6.5 --- """A Practical Methodology for Early Buffer and Wire Re- source Allocation""" --- p.35 / Chapter 3.7 --- Summary --- p.36 / Chapter 4 --- Floorplanner with Fixed Buffer Planning [34] --- p.37 / Chapter 4.1 --- Introduction --- p.37 / Chapter 4.2 --- Overview of the Floorplanner --- p.38 / Chapter 4.3 --- Congestion Model --- p.38 / Chapter 4.3.1 --- Construction of Grid Structure --- p.39 / Chapter 4.3.2 --- Counting the Number of Routes at a Grid --- p.40 / Chapter 4.3.3 --- Buffer Location Computation --- p.41 / Chapter 4.3.4 --- Counting Routes with Blocked Grids --- p.42 / Chapter 4.3.5 --- Computing the Probability of Net Crossing --- p.43 / Chapter 4.4 --- Time Complexity --- p.44 / Chapter 4.5 --- Simulated Annealing --- p.45 / Chapter 4.6 --- Wirelength Estimation --- p.46 / Chapter 4.6.1 --- Center-to-center Estimation --- p.47 / Chapter 4.6.2 --- Corner-to-corner Estimation --- p.47 / Chapter 4.6.3 --- Intersection-to-intersection Estimation --- p.48 / Chapter 4.7 --- Multi-pin Nets Handling --- p.49 / Chapter 4.8 --- Experimental Results --- p.50 / Chapter 4.9 --- Summary --- p.51 / Chapter 5 --- Floorplanner with Flexible Buffer Planning [35] --- p.53 / Chapter 5.1 --- Introduction --- p.53 / Chapter 5.2 --- Overview of the Floorplanner --- p.54 / Chapter 5.3 --- Congestion Model --- p.55 / Chapter 5.3.1 --- Probabilistic Model with Variable Interval Buffer Inser- tion Constraint --- p.57 / Chapter 5.3.2 --- Time Complexity --- p.61 / Chapter 5.4 --- Buffer Planning --- p.62 / Chapter 5.4.1 --- Estimation of Buffer Usage --- p.62 / Chapter 5.4.2 --- Estimation of Buffer Resources --- p.69 / Chapter 5.5 --- Two-phases Simulated Annealing --- p.70 / Chapter 5.6 --- Wirelength Estimation --- p.72 / Chapter 5.7 --- Multi-pin Nets Handling --- p.73 / Chapter 5.8 --- Experimental Results --- p.73 / Chapter 5.9 --- Remarks --- p.76 / Chapter 5.10 --- Summary --- p.76 / Chapter 6 --- Global Router --- p.77 / Chapter 6.1 --- Introduction --- p.77 / Chapter 6.2 --- Overview of the Global Router --- p.77 / Chapter 6.3 --- Buffer Insertion Constraint and Congestion Constraint --- p.78 / Chapter 6.4 --- Multi-pin Nets Handling --- p.79 / Chapter 6.5 --- Routing Methodology --- p.79 / Chapter 6.6 --- Implementation --- p.80 / Chapter 6.7 --- Summary --- p.86 / Chapter 7 --- Interconnect-Driven Floorplanning by Alternative Packings --- p.87 / Chapter 7.1 --- Introduction --- p.87 / Chapter 7.2 --- Overview of the Method --- p.87 / Chapter 7.3 --- Searching Alternative Packings --- p.89 / Chapter 7.3.1 --- Rectangular Supermodules in Sequence Pair --- p.89 / Chapter 7.3.2 --- Finding rearrangable module sets --- p.90 / Chapter 7.3.3 --- Alternative Sequence Pairs --- p.94 / Chapter 7.4 --- Implementation --- p.97 / Chapter 7.4.1 --- Re-calculation of Interconnect Cost --- p.98 / Chapter 7.4.2 --- Cost Function --- p.101 / Chapter 7.4.3 --- Time Complexity --- p.101 / Chapter 7.5 --- Experimental Results --- p.101 / Chapter 7.6 --- Summary --- p.103 / Chapter 8 --- Conclusion --- p.105 / Bibliography --- p.107