In search of higher speed and integration, the integrated circuit (IC) technology is scaling down. The total on-chip interconnect length is increasing exponentially. In fact, interconnect takes up the most part of the total chip area. The parasitics associated with these interconnect have significant impact on the circuit performance. Some of the effects of parasitics include cross talk, voltage drop and high current density. These issues can result in cross-talk induced functional failure and failures due to IR drop and electro-migration. This has resulted in interconnect- driven design trend in state-of-the-art integrated circuits. Reliability analysis, that includes simulating the effects of parasitics for voltage drop, current density, has become one of the most important steps in the VLSI design flow. Most of the CAD/EDA tools available, map these analysis results two dimensionally. Al- though this helps the designer, providing a three dimensional view of these results is highly desirable when dealing with complex circuits. In pursuit of visualizing reliability analysis results three dimensionally, as a first step, this work presents a tool that can visualize IC interconnect three di- mensionally. Throughout the course of this research open source tools were used to achieve the objective. In this work the circuit layout is stored as an OpenAc- cess database. A C++ program reads the design information using OpenAccess API and converts it to the .OBJ file format. Art of Illusion, an open source 3D modeling and rendering tool, reads this .OBJ file and models the IC interconnect three-dimensionally. In addition, Eclipse, an open source java IDE is used as a development platform. The tool presented has the capability to zoom in, zoom out and pan in real time.

<p> This thesis presents the results of an investigation of an integrated direct coupled grounded gyrator. A complete analysis is presented for the gyrator using components available in integrated circuit form. Integrated circuit layout and fabrication procedures are discussed. </p> <p> Close agreement between theoretical and experimental results is shown. The Q factor of a simulated inductor shows good stability over a wide range of frequency, temperature, and voltage supply. </p> / Thesis / Master of Engineering (ME)

The rapid development of wireless applications has created a demand for low-cost, compact, low-power hardware solutions. This demand has driven efforts to realize fully integrated, "single-chip" systems. While substantial progress had been made in the integration of many RF and baseband processing elements through the development of new technologies and refinements of existing technologies, progress in the area of fully monolithic filters has been limited due to the losses (low Qs) associated with integrated passive elements in standard IC processes. The work in this thesis focuses on the development low-loss, Q-enhanced LC filters in GaAs E/D-SAGFET technology. This thesis presents a methodology for designing Q-enhanced LC resonators and low-loss, monolithic LC filters based on these resonators. The first phase of this work focused on the Q-enhancement of LC resonator structures using FET-based active negative resistance circuits. Three passive resonators were designed, fabricated, and measured to determine their loss and frequency response. Furthermore, six Q-enhanced resonators were designed, fabricated, and measured to compare the performance of various negative resistance circuit designs. In the second phase of this work, four of these Q-enhanced resonator designs were used to implement fully-integrated second-order Butterworth bandpass filters. Each filter was designed for a 60 MHz, -3 dB bandwidth centered at 1.88 GHz, corresponding to the North American PCS transmit band. The best filter design achieves 0 dB of passband insertion loss while consuming 16 mA of current from a 3 V source (48 mW). Passband gain (up to 15 dB) can be achieved with increased bias current before instability is encountered. The filter provides more than 30 dB of rejection at 1.7 and 2 GHz and more than 70 dB of rejection below 1.5 GHz. In the filter passband, the noise figure is 12 dB and the output 1 dB compression point is -18 dBm. These Q-enhanced LC filters have potential application as image-reject filters in GaAs integrated transceiver designs. / Master of Science

The explosive growth in wireless communications has led to an increased demand for wireless products that are cheaper, smaller, and lower power. Recently there has been an increased interest in using CMOS, a traditional digital and low frequency analog IC technology, to implement RF components such as mixers, voltage controlled oscillators (VCOs), and low noise amplifiers (LNAs). Future mass-market RF links, such as BlueTooth, will require the potentially low-cost single-chip solutions that CMOS can provide. In order for such single-chip solutions to be realized, RF circuits must be designed that can operate in the presence of noisy digital circuitry. The voltage controlled oscillator (VCO), an important building block for RF systems, is particularly sensitive when exposed to an electrically noisy environment. In addition, CMOS implementations of VCOs have been hampered by the lack of high-quality integrated inductors. This thesis focuses on the design of a fully integrated 2.5 GHz LC CMOS VCO. The circuit is intended as a vehicle for future mixed RF/digital noise characterization. The circuit was implemented in a 0.35 μm single poly, 4 metal, 3.3 V, CMOS process available through MOSIS. The oscillator uses a complementary negative transconductance topology. This oscillator circuit is analyzed as a negative-resistance oscillator. Monolithic inductors are designed using full-wave electromagnetic field solver software. The design of an "inversion-mode" MOS (I-MOS) tuning varactor is presented, along with a discussion of the effects of varactor nonlinearity on VCO performance. I-MOS varactors are shown to have substantially improved tuning range (and tuning curve linearity) over conventional MOS varactors. Practical issues pertaining to CMOS VCO circuit design, layout, and testing are also discussed. The characterization of the VCO and the integrated passives is presented. The VCO achieves a best-case phase noise of -106.7 dBc/Hz at 100 kHz offset from a center frequency of 2.73 GHz. The tuning range is 425 MHz (17%). The circuit consumes 9 mA from a 3.3 V supply. This represents excellent performance for CMOS oscillator designs reported at this frequency. Finally, several recommendations for improvements in oscillator performance and characterization are discussed. / Master of Science

Over the past decade there has been an explosion in the demand for wireless mobile personal communications systems (PCS), a trend that shows no signs of slowing down in the foreseeable future. This demand has created a greater need for low-cost, low-power, compact system solutions. As a result, "single-chip" implementations of wireless functions have received a significant amount of attention. A significant roadblock to complete integration of these functions is the requirement for high-Q resonators in RF filter and tank circuits. Current on-chip techniques being used to realize monolithic RF resonators based on planar inductors, capacitors and active circuits are accompanied by problems such as high loss, large chip area and high power consumption. An alternative to these on-chip solutions is the use of monolithically integrated electromechanical devices. This thesis describes the modeling, fabrication and characterization of nanoelectromechanical (NEM) single crystal silicon resonators. The potential advantages associated with these devices are high-Q, small die area and low power consumption. The development of such devices compatible with modern integrated circuit fabrication techniques offers the possibility for integration of high performance RF filters and resonators onto a single RFIC chip. The advantageous characteristics of these resonators could lead to mobile PCS devices with lower cost and increased battery life. The NEM resonator designs investigated in this work are fabricated using an electron-beam lithography based surface machining process in silicon-on-insulator technology. Various design, fabrication and testing issues are discussed. The feasibility of lateral capacitive actuation and detection in such structures is examined. / Master of Science

No description available.

Abstract The developing trend toward the integreation of many function in application market of semiconductor, makes the original business model of IC design industry to change. From open structure (named ¡§Wintel¡¨ structure) till today, what we can see it shows as transition stage. It will be end in the situation the all devices can interlink to each other. All of us don¡¦t know how long we will overcome this transition stage. But it really challenges the orginal business model of IC design industry. The business model of IC design industry changes along with the changing in product application market. In this study, we do analysis of IC design industry¡¦s business model by four dimensions¡Xmarket strategies, capabilities of technology, the types of organization, financial resources. We will discuss the differents between Taiwan and American IC design industry In market strategy dimension, there are more and more difficults to distinguish between past strategy model including niche and volume strategies. Because the revolution of electronics application market, the better ways for Taiwan IC design industry to develop its market strategy are depending on capability focusing and the capture of market demend. When mentioning about the IC design skill, Taiwan IC design industry can choose several ways to cumulate its design capabilities according to the market strategy it chose. About types of the organization, the combination of fabless and fabless is the trend. Also 1¡¦st tier IDM will be the key roles who dominate the future IC industry. More than all, fabless who belong to system assembly factory or fabless who belong to foundry will be the mainstream in the IC industry and in electronics application market, too. Depending on what kinds of organzation IC design companies chose, it will affect the ability when they rising money. These four factors interaction built the business model of the Taiwan IC design industry.

No description available.

L’équipe de conception de Freescale à Toulouse développe des circuits intégrés dédiés au marché de l’automobile pour des applications châssis, sécurité ou loisir. Les contraintes associées à l’embarquement des circuits sont nombreuses : niveau d’intégration, fiabilité, températures élevées, et compatibilité électromagnétique. Les produits conçus par Freescale intègrent des convertisseurs à découpage pour l’alimentation en énergie des microcontrôleurs. Cette thèse a pour objet l’étude de nouvelles topologies de convertisseur d’énergie pour la baisse de l’encombrement et des perturbations électromagnétiques. La structure multiphase répond à la problématique dans son ensemble. Un prototype est réalisé dans une technologie silicium Freescale haute tension 0.25µm. Le volume des composants externes de filtrage est optimisé et réduit. Les mesures sur le prototype montrent des performances en accord avec les objectifs, et des émissions électromagnétiques particulièrement faibles. / The Freescale design team in Toulouse develops integrated circuits for automotive application such as chassis, safety or infotainment. Constraints associated with the embodiment of such circuits are many: die-size, safety, EMC (Electromagnetic Compliance). Switching Mode Power Supplies are integrated in these products to supply power to microcontrollers. This PhD thesis is to study new topologies of power supply to reduce the volume and electromagnetic disturbances. The multiphase structure responds to the raised issue. A prototype is produced in a Freescale 0.25µm high voltage silicon technology. Volume of the external components for filtering is optimized and reduced. Measures show upgrades in performance and reduced electromagnetic emissions.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / To meet specific test and evaluation requirements, the Hardened Subminiature Telemetry and Sensor Systems (HSTSS) program is addressing the miniaturization and ‘G’ hardening of telemetry components. Two custom Integrated Circuits (ICs) are in development to support the design of miniature Pulse Code Modulation (PCM) systems with up to 128 analog input channels. This paper describes the design and development of the custom IC chips of the HSTSS Data Acquisition Chipset (DAC). The original requirements, the roll of the Integrated Product Team (IPT), design decisions, a discussion of the additional features, and practical limitations of the Data Acquisition Chipset will be covered.