Stress induced void formation in Cu interconnects, due to thermal stresses generated during the processing of semiconductors, is an increasing reliability issue in the semiconductor industry as Cu interconnects are being downscaled to follow the demand for faster chip speed. In this work, 1.8 micron and 180 nm wide Cu interconnects, fabricated by Freescale Semiconductors, were subjected to thermal cycles, in-situ in the TEM, to investigate the stress relaxation mechanisms as a function of interconnect linewidth. The experiments show that the 1.8 micron Cu interconnect lines relax the thermal stresses through dislocation nucleation and motion while the Cu interconnect 180 nm lines exhibit void formation. Void formation in 180 nm lines occurs predominantly at triple junctions where the Ta diffusion barrier meets a Cu grain boundary. In order to understand void formation in 180 nm lines, the grain orientation and local stresses are determined. In particular, Nanobeam Diffraction (NBD) in the TEM is used to obtain the diffraction pattern of each grain, from which the crystal orientation is evaluated by the ACT (Automated Crystallography for TEM) software. In addition, 2D Finite Element Method (FEM) simulations are performed using the Object Oriented Finite Modeling (OOF2) software to correlate grain orientation with local stresses, and consequently void formation. According to the experimental and simulation results obtained, void formation in 180nm Cu interconnects does not seem to be solely dependent on local stresses, but a combination of diffusion paths available, stress gradients and possibly the presence of defects. In addition, based on the in-situ TEM observations, void growth seems to occur through grain boundary and/or interfacial diffusion. However, in-situ STEM observations of fully opened voids post-failure show pileup of material at the Cu grain surfaces. This means that surface or interface diffusion is also very active during void growth in the presence of thermal stresses.

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Differential interconnects are extensively used in high-speed digital circuits at fast data rates and in environments of high noise like backplanes. For such applications they are preferred over single-ended lines owing to their ability to reject common-mode noise. Differential schemes like Low Voltage Differential Signaling (LVDS) are used for wireless base stations and ATM switches in telecommunication applications, flat panel displays and servers and for system-level clock distribution. LVDS applications use data rates from 100 Mbps to about 1.5 Gbps and are expected to be highly immune to noise. However, noise will also be injected into differential signals at these high data rates, if there are irregularities in the interconnect setup. These anomalies may be via transitions from differential lines through power planes in power distribution systems, via stubs, asymmetric lengths of differential lines, different transition points for each of the differential vias etc. The differential setup is expected to be immune to such imbalances; however, investigation of these discontinuities indicate that sufficient signal energy can be leaked to power distribution networks (PDN) of packages and boards. The effect of this energy loss was examined in time-domain and was found to cause signal integrity effects like jitter. Irregular differential structures were compared with the equivalent single-ended configuration and symmetrical perfect differential lines. This thesis work quantifies signal to power coupling caused by irregular differential structures in the presence of PDN planes in frequency domain. Presence of noise in differential signaling is verified through a set of test vehicles. The jitter induced as a result of signal to power coupling from differential lines was also investigated.

A high-performance 2D or 3D integrated circuit typically has (i) ratio of delay of a 1mm wire to delay of a nMOS transistor > 500, (ii) target impedence of power delivery network < 1mΩ, (iii) clock frequency > 2GHz, and (iv) thermal resistance requirement of heat removal path < 0.6 degree C/W. This data illustrates the difficulty of obtaining high-quality signal, power, clock and thermal interconnect networks for gigascale 2D and 3D integrated circuits. Specific material, process, circuit, packaging, and architecture solutions to enhance these four types of interconnect networks are proposed and quantitatively evaluated. A microchannel-cooled 3D integrated circuit technology is developed to deal with thermal interconnect problems inherent to stacked dice. The benefits of carbon nanotube technology, improved repeater insertion techniques and parallel processing architectures for signal interconnect networks are evaluated. A circuit technique to periodically reverse current direction in power interconnect networks is proposed. It provides several orders of magnitude improvement in electromigration lifetimes. Methods to control power supply noise and reduce its impact on clock interconnect networks are investigated. Finally, a CAD tool to co-design signal, power, clock and thermal interconnect networks in high-performance 2D and 3D integrated circuits is developed.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (M. Phil.)--University of Hong Kong, 2008. / Also available in print.

Thesis (M. S.)--Materials Science and Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Rao R. Tummala; Committee Member: C. P. Wong; Committee Member: P. M. Raj.