Depuis la commercialisation du premier circuit intégré en 1971, l'industrie de la microélectronique s'est fixée comme leitmotiv de réduire les dimensions des transistors MOSFETs, en suivant la loi de Moore. Comme indiqué par Dennard, cette miniaturisation améliore automatiquement les performances des transistors. A partir des nœuds 28-22nm, les effets canaux courts sont trop difficiles à contrôler et de nouvelles architectures de transistors sont introduites: FDSOI pour STMicroelectronics, Trigate pour Intel. Dans ce contexte, l'évaluation des performances des technologies CMOS est clé et les travaux de cette thèse proposent de les évaluer au niveau circuit. Des modèles spécifiques d'estimation des paramètres électrostatiques et des capacités parasites sont développés. Ceux-ci sont d'abord utilisés sur des technologies amonts (co-intégration III-V/Ge et intégration 3D) puis sont implémentés en VerilogA pour être utilisés avec les outils conventionnel de CAO. Ceci fournit un modèle compact prédictif et utilisable pour toutes les architectures CMOS, qui est utilisé pour évaluer les performances logiques et SRAM des architectures BULK, FDSOI et Trigate aux nœuds 20nm et 16nm. / Since the commercialization of the first integrated circuit in 1971, the microelectronic industry has fixed as an objective to reduce MOSFET transistor dimensions, following Moore's law. As indicated by Dennard, this miniaturization automatically improves device performances. Starting from the 28-22nm technological nodes, short channel effects are to strong and industrial companies choose to introduce new device structure: FDSOI for STMicroelectronics and Trigate for Intel. In such a context, CMOS technology performance evaluation is key and this thesis proposes to evaluate them at circuit level. Specific models for electrostatic parameters and parasitic capacitances for each device structure are developed for each device structure. Those models have first been used to evaluate performances of advanced technologies, such as III-V/Ge co-integration and 3D monolithic integration and have then been implemented in VerilogA to ensure compatibility with conventional CAD tools such as ELDO. This provides a compact model, predictive and usable for each device structure, which has been used to evaluated logic and SRAM performances of BULK, FDSOI and Trigate devices for the 20nm and 16nm technology node.

O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa miniaturização permitiu a construção de dispositivos menores, mais rápidos e que consomem menos frequência. O outro fator é a utilização da metodologia baseada em biblioteca de células. Esta metodologia permite o projeto de um circuito eficiente em um curto espaço de tempo. Com a redução dos dispositivos, novos fatores que eram desconsiderados no fluxo automático passaram a ter importância. Dentre eles podemos citar o consumo estático, a variabilidade, a manufaturabilidade e o envelhecimento. Alguns desses fatores, como o consumo estático e a variabilidade, já estão integrados à metodologia baseada em biblioteca de células. Os efeitos de envelhecimento tem sua degradação aumentada a cada novo processo tecnológico, assim como tem aumentado também a sua importância em relação à confiabilidade do circuito ao longo da sua vida útil. Este trabalho irá explorar estes efeitos de envelhecimento no projeto de circuitos integrados digitais. Dentre as principais contribuições pode-se destacar a definição de um custo de envelhecimento na definição de portas lógicas, que pode ser explorado pelos algoritmos de síntese lógica para obterem um circuito mais confiável. Este custo também pode ser utilizado pelas ferramentas de análise a fim de obter uma estimativa da degradação que o circuito proposto irá sofrer ao longo da sua vida útil. Além disso, é apresentada uma proposta de reordenamento estrutural do arranjo de transistores em portas lógicas, a fim de tratar os efeitos de envelhecimento nos níveis mais iniciais do fluxo. Por fim, uma análise simplificada de características a serem exploradas ao nível de circuito é discutida utilizando o auxílio do projeto de portas lógicas complexas. Os resultados apresentam uma boa e rápida estimativa da degradação das portas lógicas. A reestruturação do arranjo dos transistores tem se apresentado como uma boa alternativa ao projeto de circuitos mais confiáveis. Além disso, a utilização de arranjos mais complexos também é uma excelente alternativa que explora a robustez intrínseca da associação de transistores em série. Além disso, as alternativas propostas podem ser utilizadas em conjunto com técnicas já existentes na literatura. / The increased presence of integrated circuit (IC) in the people’s life has occurred for main two reasons. The first is the aggressive scaling of integrated device dimensions. This miniaturization enabled the construction of smaller, faster and lower power consumption devices. The other factor is the use of a cell based methodology in IC design. This methodology is able to provide efficient circuits in a short time. With the devices scaling, new factors that were usually ignored in micrometer technologies have become relevant in nanometer designs. Among them, it can be mentioned the static consumption, process parameters variability, manufacturability and aging effects. Some of these factors, such as static consumption and variability, are already taken into account by the standard cell design methodology. On the other hand, the degradation caused by aging effects has increased at each new technology node, as well as the importance in relation to the circuit reliability throughout its entire lifetime has also increased. This thesis explores such aging effects in the design of digital IC. The main contributions can be highlighted as the definition of a cost of aging that can be exploited by logic synthesis algorithms to produce a more reliable circuit. This cost can be also used by the analysis tools in order to obtain an estimative of the degradation that specific circuit experiences throughout their lifetime. In addition, a proposal to reorder the transistor structural arrangement of logic gates is presented in order to treat the effects of aging on initial steps in the design flow. Finally, a simplified analysis of the characteristics to be exploited at circuit level is performed exploring details of the design of complex logic gates. The aging cost results have given a good and fast prediction of logic gates degradation. The transistor arrangement restructuring approach is a good alternative to design more reliable circuits. Furthermore, the use of complex arrangements is also an excellent alternative which exploits the intrinsic robustness of series transistors association. Moreover, the discussed approaches can be easily used together with existing techniques in the literature to achieve better results.

O avanço das tecnologias de circuitos integrados (CIs) levanta importantes questões relacionadas à confiabilidade e à robustez de sistemas eletrônicos. A diminuição da geometria dos transistores, a redução dos níveis de tensão, as menores capacitâncias e portanto menores correntes e cargas para alimentar os circuitos, além das freqüências de relógio elevadas, têm tornado os CIs mais vulneráveis a falhas, especialmente àquelas causadas por ruído elétrico ou por efeitos induzidos pela radiação. Os efeitos induzidos pela radiação conhecidos como Soft Single Event Effects (Soft SEEs) podem ser classificados em: Single Event Upsets (SEUs) diretos em nós de elementos de armazenagem que resultam em inversões de bits; e pulsos transientes Single Event Transients (SETs) em qualquer nó do circuito. Especialmente SETs em circuitos combinacionais podem se propagar até os elementos de armazenagem e podem ser capturados. Estas errôneas armazenagens podem também serem chamadas de SEUs indiretos. Falhas como SETs e SEUs podem provocar erros em operações funcionais de um CI. Os conhecidos Soft Errors (SEs) são caracterizados por valores armazenados erradamente em elementos de memória durante o uso do CI. SEs podem produzir sérias conseqüências em aplicações de CIs devido à sua natureza não permanente e não recorrente. Por essas razões, mecanismos de proteção para evitar SEs através de técnicas de tolerância a falhas, no mínimo em um nível de abstração do projeto, são atualmente fundamentais para melhorar a confiabilidade de sistemas. Neste trabalho de dissertação, uma versão tolerante a falhas de um microprocessador 8-bits de produção em massa da família M68HC11 foi projetada. A arquitetura é capaz de tolerar SETs e SEUs. Baseado nas técnicas de Redundância Modular Tripla (TMR) e Redundância no Tempo (TR), um esquema de proteção foi projetado e implementado em alto nível no microprocessador alvo usando apenas portas lógicas padrões. O esquema projetado preserva as características da arquitetura padrão de tal forma que a reusabilidade das aplicações do microprocessador é garantida. Um típico fluxo de projeto de circuitos integrados foi desenvolvido através de ferramentas de CAD comerciais. Testes funcionais e injeções de falhas através da simulação de execuções de benchmarks foram realizados como um teste de verificação do projeto. Além disto, detalhes do projeto do circuito integrado tolerante a falhas e resultados em área, performance e potência foram comparados com uma versão não protegida do microprocessador. A área do core aumentou 102,64 % para proteger o circuito alvo contra SETs e SEUs. A performance foi degrada em 12,73 % e o consumo de potência cresceu cerca de 49 % para um conjunto de benchmarks. A área resultante do chip robusto foi aproximadamente 5,707 mm². / The advance of the IC technologies raises important issues related to the reliability and robustness of electronic systems. The transistor scale by shrinking its geometry, the voltage reduction, the lesser capacitances and therefore smaller currents and charges to supply the circuits, besides the higher clock frequencies, have made the IC more vulnerable to faults, especially those faults caused by electrical noise or radiationinduced effects. The radiation-induced effects known as Soft Single Event Effects (Soft SEEs) can be classified into: direct Single Event Upsets (SEUs) at nodes of storage elements that result in bit flips; and Single Event Transient (SET) pulses at any circuit node. Especially SETs on combinational circuits might propagate itself up to the storage elements and might be captured. These erroneous storages can be also called indirect SEUs. Faults like SETs and SEUs can provoke errors in functional operations of an IC. The known Soft Errors (SEs) are characterized by values stored wrongly on memory elements during the use of the IC. They can make serious consequences in IC applications due to their non-permanent and non-recurring nature. By these reasons, protection mechanisms to avoid SEs by using fault-tolerance techniques, at least in one abstraction level of the design, are currently fundamental to improve the reliability of systems. In this dissertation work, a fault-tolerant IC version of a mass-produced 8-bit microprocessor from the M68HC11 family was designed. It is able to tolerate SETs and SEUs. Based on the Triple Modular Redundancy (TMR) and Time Redundancy (TR) fault-tolerance techniques, a protection scheme was designed and implemented at high level in the target microprocessor by using only standard logic gates. The designed scheme preserves the standard-architecture characteristics in such way that the reusability of microprocessor applications is guaranteed. A typical IC design flow was developed by means of commercial CAD tools. Functional testing and fault injection simulations through benchmark executions were performed as a design verification testing. Furthermore, fault-tolerant IC design issues and results in area, performance and power were compared with a non-protected microprocessor version. The core area increased by 102.64 % to protect the target circuit against SETs and SEUs. The performance was degraded in 12.73 % and the power consumption grew around 49 % for a set of benchmarks. The resulting area of the robust chip was approximately 5.707 mm².

O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa miniaturização permitiu a construção de dispositivos menores, mais rápidos e que consomem menos frequência. O outro fator é a utilização da metodologia baseada em biblioteca de células. Esta metodologia permite o projeto de um circuito eficiente em um curto espaço de tempo. Com a redução dos dispositivos, novos fatores que eram desconsiderados no fluxo automático passaram a ter importância. Dentre eles podemos citar o consumo estático, a variabilidade, a manufaturabilidade e o envelhecimento. Alguns desses fatores, como o consumo estático e a variabilidade, já estão integrados à metodologia baseada em biblioteca de células. Os efeitos de envelhecimento tem sua degradação aumentada a cada novo processo tecnológico, assim como tem aumentado também a sua importância em relação à confiabilidade do circuito ao longo da sua vida útil. Este trabalho irá explorar estes efeitos de envelhecimento no projeto de circuitos integrados digitais. Dentre as principais contribuições pode-se destacar a definição de um custo de envelhecimento na definição de portas lógicas, que pode ser explorado pelos algoritmos de síntese lógica para obterem um circuito mais confiável. Este custo também pode ser utilizado pelas ferramentas de análise a fim de obter uma estimativa da degradação que o circuito proposto irá sofrer ao longo da sua vida útil. Além disso, é apresentada uma proposta de reordenamento estrutural do arranjo de transistores em portas lógicas, a fim de tratar os efeitos de envelhecimento nos níveis mais iniciais do fluxo. Por fim, uma análise simplificada de características a serem exploradas ao nível de circuito é discutida utilizando o auxílio do projeto de portas lógicas complexas. Os resultados apresentam uma boa e rápida estimativa da degradação das portas lógicas. A reestruturação do arranjo dos transistores tem se apresentado como uma boa alternativa ao projeto de circuitos mais confiáveis. Além disso, a utilização de arranjos mais complexos também é uma excelente alternativa que explora a robustez intrínseca da associação de transistores em série. Além disso, as alternativas propostas podem ser utilizadas em conjunto com técnicas já existentes na literatura. / The increased presence of integrated circuit (IC) in the people’s life has occurred for main two reasons. The first is the aggressive scaling of integrated device dimensions. This miniaturization enabled the construction of smaller, faster and lower power consumption devices. The other factor is the use of a cell based methodology in IC design. This methodology is able to provide efficient circuits in a short time. With the devices scaling, new factors that were usually ignored in micrometer technologies have become relevant in nanometer designs. Among them, it can be mentioned the static consumption, process parameters variability, manufacturability and aging effects. Some of these factors, such as static consumption and variability, are already taken into account by the standard cell design methodology. On the other hand, the degradation caused by aging effects has increased at each new technology node, as well as the importance in relation to the circuit reliability throughout its entire lifetime has also increased. This thesis explores such aging effects in the design of digital IC. The main contributions can be highlighted as the definition of a cost of aging that can be exploited by logic synthesis algorithms to produce a more reliable circuit. This cost can be also used by the analysis tools in order to obtain an estimative of the degradation that specific circuit experiences throughout their lifetime. In addition, a proposal to reorder the transistor structural arrangement of logic gates is presented in order to treat the effects of aging on initial steps in the design flow. Finally, a simplified analysis of the characteristics to be exploited at circuit level is performed exploring details of the design of complex logic gates. The aging cost results have given a good and fast prediction of logic gates degradation. The transistor arrangement restructuring approach is a good alternative to design more reliable circuits. Furthermore, the use of complex arrangements is also an excellent alternative which exploits the intrinsic robustness of series transistors association. Moreover, the discussed approaches can be easily used together with existing techniques in the literature to achieve better results.

Orientador: Fabiano Fruett / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação / Made available in DSpace on 2018-08-16T19:24:36Z (GMT). No. of bitstreams: 1 Camolesi_Alessandro_M.pdf: 2180894 bytes, checksum: c85cabaf810d1a57424f169a1f9b2f85 (MD5) Previous issue date: 2010 / Resumo: Apresentamos neste trabalho a fabricação e a caracterização de um sensor de pressão totalmente compatível com a tecnologia CMOS. Este sensor é constituído por quatro piezoresistores, implantados e dispostos em ponte de Wheatstone. Os processos de fabricação do sensor foram todos realizados no Centro de Componentes e Semicondutores (CCS) - Unicamp. A membrana do sensor foi obtida através de um processo de desbaste mecânico do die que foi colado em uma placa de alumina. O alinhamento da colagem foi baseado em um orifício central. O sensor encapsulado apresentou sensibilidade de 0.32mV/psi. Além disso, projetamos uma fonte de referência em tensão do tipo Bandgap. Nesta fonte de referência usamos uma técnica para minimizar os gradientes de estresse mecânico, a maior fonte de não-idealidade desta fonte de referência e permitiu estudarmos a deriva térmica da sensibilidade da ponte / Abstract: We presented in this work the fabrication and the characterization of a pressure sensor totally CMOS compatible. This sensor is arranged by four p-type silicon piezoresistive implanted in a Wheatstone bridge. The fabrication processes were all performed at the Center for Components and Semiconductors (CCS) - Unicamp. The membrane was obtained by a mechanical polishing process of the die that was attached by RTV (Room Temperature Vulcanization) on an alumina substrate. The attach alignment was based on the center of the vent hole. The packaged sensor showed a sensitivity amounts to 0.32mV/psi. Also, a Bandgap voltage reference was designed. In such voltage reference uses a technical to minimize gradients such as mechanical stress, the main non-ideality source to such voltage reference and it allowed the drift thermal analysis of the bridge sensitivity / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

L’équipe de conception de Freescale à Toulouse développe des circuits intégrés dédiés au marché de l’automobile pour des applications châssis, sécurité ou loisir. Les contraintes associées à l’embarquement des circuits sont nombreuses : niveau d’intégration, fiabilité, températures élevées, et compatibilité électromagnétique. Les produits conçus par Freescale intègrent des convertisseurs à découpage pour l’alimentation en énergie des microcontrôleurs. Cette thèse a pour objet l’étude de nouvelles topologies de convertisseur d’énergie pour la baisse de l’encombrement et des perturbations électromagnétiques. La structure multiphase répond à la problématique dans son ensemble. Un prototype est réalisé dans une technologie silicium Freescale haute tension 0.25µm. Le volume des composants externes de filtrage est optimisé et réduit. Les mesures sur le prototype montrent des performances en accord avec les objectifs, et des émissions électromagnétiques particulièrement faibles.

Les travaux de thèse portent sur la conception et la réalisation d'un circuit intégré de commande rapprochée générique pour les transistors à grille isolée comme les MOSFETs et les IGBTs dans les structures de conversion d'énergie de l'électronique de puissance. L'objectif principal est de concevoir un système de commande simple à mettre en oeuvre, compact et configurable pouvant servir un panel varié d'applications dites multi-transistors. Le mémoire de thèse se structure en quatre chapitres : état de l'art de la commande rapprochée des transistors à grille isolée, présentation et validation d'une nouvelle topologie de commande rapprochée à base de transformateur d'impulsion, présentation et validation d'une version améliorée pour travailler à large spectre de fréquence et de rapport cyclique, conception et validation du driver intégré générique. Les champs d'application de ce concept du driver sont multiples, celui-ci favorise la simplicité de la conception et de la mise en oeuvre des système de commande pour l'électronique de puissance. / The thesis work focuses on the design and the implementation of a generic integrated gate driver circuit for power transistors such as MOSFETs and IGBTs in power conversion structure. The main objective is to design a control system which is simple to implement, compact and can be configurable to serve several multi-transistors applications. The thesis is structured into four chapters: state of the art of the gate driver for power transistor, presentation and validation of a new gate driver topology based on pulse transformer, presentation and validation of an upgraded version enable to work with wider range of frequency and duty cycle, design and validation of a generic integrated driver. The fields of application of this driver concept are multiples; it promotes the simplicity of the design and implementation of control system for power electronics.

The past decade witnessed the rapid development of III-nitride light-emitting diodes (LEDs) and laser diodes (LDs), for smart lighting, visible-light communication (VLC), optical storage, and internet-of-things. Recent studies suggested that the GaN-based LDs, which is free from efficiency droop, outperform LEDs as a viable high-power light source. Conventionally, the InGaN-based LDs are grown on polar, c-plane GaN substrates. However, a relatively low differential gain limited the device performance due to a significant polarization field in the active region. Therefore, the LDs grown on nonpolar m-plane and semipolar (2021)-plane GaN substrates are posed to deliver high-efficiency owing to the entirely or partially eliminated polarization field. To date, the smart lighting and VLC functionalities have been demonstrated based on discrete devices, such as LDs, transverse-transmission modulators, and waveguide photodetectors. The integration of III-nitride photonic components, including the light emitter, modulator, absorber, amplifier, and photodetector, towards the realization of III-nitride photonic integrated circuit (PIC) offers the advantages of small-footprint, high-speed, and low power consumption, which has yet to be investigated. This dissertation presents the design, fabrication, and characterization of the multi-section InGaN laser diodes with integrated functionalities on semipolar (2021)-plane GaN substrates for enabling such photonic integration. The blue-emitting integrated waveguide modulator-laser diode (IWM-LD) exhibits a high modulation efficiency of 2.68 dB/V. A large extinction ratio of 11.3 dB is measured in the violet-emitting IWM-LD. Utilizing an integrated absorber, a high optical power (250mW), droop-free, speckle-free, and large modulation bandwidth (560MHz) blue-emitting superluminescent diode is reported. An integrated short-wavelength semiconductor optical amplifier with the laser diode at ~404 nm is demonstrated with a large gain of 5.32 dB at 6 V. A high-performance waveguide photodetector integrated LD at 405 nm sharing the single active region is presented, showing a significant large modulation bandwidth of 230 MHz. Thus these seamlessly integrated elements enable photonic IC at the visible wavelength for many important applications, such as smart lighting and display, optical communication, switching, clocking, and interconnect. The findings are therefore significant in developing an energy-saving platform technology that powers up human activities in a safe, health- and environmental-friendly manner.

<div>Integrated optical phased arrays (OPAs) have gained popularity for achieving beam steering with no moving parts and potential high speed and small beam divergence angle. These characteristics are crucial for applications like free-space communication and light detection and ranging (LiDAR), a key component in autonomous driving. Two main aspects that affect the performance of an integrated OPA are discussed: high power handling and large beam steering range.</div><div><br></div><div>High emission power from the OPA is desirable for long range detection applications. Silicon is broadly used in integrated OPA designs as it allows for structures with a more compact footprint. However, its power-handling capability is limited by the two-photon absorption of the material, resulting in higher loss and potential damage at high input power levels. In this work, high power delivery into free space is realized by using a silicon nitride (SiN) and silicon hybrid platform. SiN components are used to direct and split high input power into smaller portions and coupled into silicon components for a more compact emitter array.</div><div><br></div><div>In order to achieve a full 180-degree beam steering range with aliasing-free operation, the pitch of a periodic emitter array is required to be half of the operating wavelength or less. At such a small pitch, evanescent coupling between adjacent emitters causes strong crosstalk. We demonstrate the optical phased array based on uniform half-wavelength spaced grating emitter array. Two-dimensional beam confinement and a record-high aliasing-free beam steering field-of-view of 135 degrees from grating emitter are measured from a 32 channel SiN/Si hybrid OPA. Evanescent coupling between waveguides are suppressed by metamaterial-based <b>e</b>xtreme <b>ski</b>n-<b>d</b>epth (e-skid) waveguides. The e-skid waveguides utilize an alternating air-silicon multi-fin side cladding. The high index contrast of those sub-wavelength ridges provides strong anisotropy, which leads to faster decay of the evanescent wave for transverse electric (TE) input modes, thus limiting evanescent coupling between closely spaced waveguides.</div><div><br></div><div>Furthermore, we extend the concept of the half-wavelength-pitched emitter array to the design of a two-dimensional end-fire OPA. This OPA can potentially achieve 180-degree by 180-degree full-range beam steering with no grating lobes by having a half-wavelength emitter pitch in both dimensions. The design of a broadband 8 by 8 silicon photonics switch based on the half-wavelength-pitched emitter array with low path-dependent loss (PDL) is also discussed.</div>

Operational amplifier will be designed and optimized with respect to set of required parameters. Real CMOS technology (available at Department of Microelectronics) will be used for designed OTA circuit and its simulations. Designed OTA will be used as universal operation amplifier configurable block in FPAA (field-programmable analog array) structures.