There has been increased interest in exploring high frequency (mm-wave) spectrum (particularly the 30 and 60 GHz ranges), and utilizing silicon-based technology for reduced-cost monolithic millimeter integrated circuits (MMIC), for applications such as WLAN, inter-vehicle communication (IVC) automotive radar and local multipoint distribution system (LMDS). Although there has been a significant increase in silicon-based implementations recently, this area still has significant need for research and development. For example, one microwave/mm-wave front-end component that has seen little development in silicon is the power amplifier (PA). Two potential technologies exist for providing a solution for low-cost microwave/mm-wave power amplifiers: 1) Silicon-Germanium (SiGe) HBT and 2) Complementary metal-oxide semiconductor (CMOS). SiGe HBT has become a viable candidate for PA development since it exhibits higher gain and higher breakdown voltage limits compared to CMOS, while remaining compatible with BiCMOS technology. Also, SiGe is potentially lower in cost compared to other compound semiconductor technologies that are currently used in power amplifier design. Hence, this research focuses on design of millimeter-wave power amplifiers in SiGe HBT technology. The work presented in this thesis will focus on design of different power amplifiers for millimeter-wave operating frequencies. Amplifiers present the fundamental trade-off between linearity and efficiency. Applications at frequencies highlighted above tend to be point-to-point, and hence high linearity is required at the cost of lowered efficiency for these power amplifiers. The designed power amplifiers are fully differential topologies based on finite ground coplanar waveguide (FGC) transmission line technology, and have on-chip matching networks and bias circuits. The selection and design of FGC lines is supported through full-wave EM simulations. Tuned single stub matching networks are realized using FGC technology and utilized for input and output matching networks. Two 30-GHz range SiGe HBT PA designs were carried out in Atmel SiGe2RF and IBM BiCMOS 8HP IC technologies. The designs were characterized first by simulations. The performance of the Atmel PA design was characterized using microwave/mm-wave on wafer test measurement setup. The IBM 8HP design is awaiting fabrication. The measured results indicated high linearity, targeted output power range, and expected efficiency performance were achieved. This validates the selection of SiGe HBT as the technology of choice of high frequency point-to-point applications. The results show that it is possible to design power amplifiers that can effectively work at millimeter-wave frequencies at lower cost for applications such as mm-wave WLAN and IVC where linearity is important and required transmitted power is much lower than in cellular handset power amplifiers. Moreover, recommendations are made for future research steps to improve upon the presented designs. / Master of Science

The recent trend in modern information technology has been towards the increased use of portable and handheld devices such as cellular telephones, personal digital assistants (PDAs), and wireless networks. This trend presents the need for compact and power efficient radio systems. Typically, the most power inefficient device in a radio system is the power amplifier (PA). PA inefficiency requires increased battery reserves to supply the necessary DC bias current, resulting in larger devices. Alternatively, the length of time between battery charges is reduced for a given battery size, reducing mobility. In addition, communications channels are becoming increasingly crowded, which presents the need for improved bandwidth efficiency. In order to make more efficient use of the frequency spectrum allocated for a particular system, there is a push towards complex higher order digital modulation schemes in modern radio systems, resulting in stricter linearity requirements on the system. Since power efficient amplifiers are typically nonlinear, this poses a major problem in realizing a bandwidth and power efficient radio system. However, by employing various linearization techniques, the linearity of a high efficiency PA may be improved. The work presented in this thesis focuses on diode predistortion linearization, particularly for PA RFICs in digital radios. Background discussion on common linearization techniques available to the PA designer is presented. In addition, a discussion of traditional and modern methods of nonlinearity characterization is presented, illustrating the nonlinear PA effects on a modulated signal. This includes the use of two-tone analysis and the more modern envelope analysis. The operation of diode predistortion linearizers is discussed in detail, along with diode optimization procedures for PA linearization with minimum impact on return loss and gain. This diode optimization is effective in improving the ability to integrate the predistorter into a single, linearized PA RFIC chip. MESFET and HBT based diode linearizers are studied for use with corresponding MESFET and HBT based PAs in the 2.68 GHz and 1.95 GHz frequency bands, respectively. Results show an improvement in adjacent channel power ratio (ACPR) due to the linearizer in both MESFET and HBT cases. A fully integrated 1.95 GHz linearizer and PA RFIC in HBT technology is also presented. Design considerations, simulations, and layouts for this design are presented. Finally, several recommendations are made for continued research in this area. / Master of Science

In 1997 the Federal Communications Commission (FCC) released 300 MHz of spectrum between 5-6 GHz designated the unlicensed national information infrastructure (U-NII) band. The intention of the FCC was to provide an unlicensed band of frequencies that would enable high-speed wireless local area networks (WLANs) and facilitate wireless access to the national information infrastructure with a minimum interference to other devices. Currently, there is a lack of cost-effective technologies for developing U-NII band components. With the commercial market placing emphasis on low cost, low power, and highly integrated implementations of RF circuitry, alternatives to the large and expensive distributed element components historically used at these frequencies are needed. Silicon Germanium (SiGe) BiCMOS technology represents one possible solution to this problem. The SiGe BiCMOS process has the potential for low cost since it leverages mature Si process technologies and can use existing Si fabrication infrastructure. In addition, SiGe BiCMOS processes offer excellent high frequency performance through the use of SiGe heterojunction bipolar transistors (HBTs), while coexisting Si CMOS offers compatibility with digital circuitry for high level 'system-on-a-chip' integration. The work presented in this thesis focuses on the development of a SiGe RFIC front-end for operation in the U-NII bands. Specifically, three variants of a packaged low noise amplifier (LNA) and a packaged active x2 sub-harmonic mixer (SHM) have been designed, simulated and measured. The fabrication of the Rifts was through the IBM SiGe foundry; the packaging was performed by RF Micro devices. The mixer and LNA designs were fabricated on separate die, packaged individually, and on-chip matched to a 50 ohm system so they could be fully characterized. Measurements were facilitated in a coaxial system using standard FR4 printed circuit boards. The LNA designs use a single stage, cascoded topology. The input ports are impedance matched using inductive emitter degeneration through bondwires to ground. One version of the LNA uses an shunt inductor/series capacitor output match while the other two variation use a series inductor output match. Gain, isolation, match, linearity and noise figure (NF) were used to characterize the performance of the LNAs in the 5 - 6 GHz frequency band. The best LNA design has a maximum gain of 9 dB, an input VSWR between 1.6:1 and 2:1, an output match between 1.7:1 and 3.6:1, a NF better than 3.9 dB and an input intercept point (IIP3) greater than 5.4 dBm. The LNA operates from a 3.3 V supply voltage and consumes 4 mA of current. The SHM is an active, double-balance mixer that achieves x2 sub-harmonic mixing through two quadrature (I/Q) driven, stacked Gilbert-cell switching stages. Single-ended-to-differential conversion, buffering and I/Q phase separation of the LO signal are integrated on-chip. Measurements were performed to find the optimal operating range for the mixer, and the mixer was characterized under these sets of conditions. It was found that the optimal performance of the mixer occurs at an IF of 250-450 MHz and an LO power of -5 dBm. Under these conditions, the mixer has a measured conversion gain of 9.3 dB, a P_1-dB of -15.7 dBm and an 2LO/RF isolation greater than 35 dB at 5.25 GHz. At 5.775 GHz, the conversion gain is 7.7 dB, the P_1-dB is -15.0 dBm, and the isolation is greater than 35 dB. The mixer core consumes 9.5 mA from a 5.0 V supply voltage. This work is sponsored by RF Microdevices (RFMD)through the CWT affiliate program.The author was supported under a Bradley Foundation fellowship. / Master of Science

In this modern age of information, the demands on data transmission networks for greater capacity, and mobile accessibility are increasing drastically. The increasing demand for mobile access is evidenced by the proliferation of wireless systems such as mobile phone networks and wireless local area networks (WLANs). The frequency range over which an oxygen resonance occurs in the atmosphere (~58-62 GHz) has received recent attention as a possible candidate for secure high-speed wireless data networks with a potentially high degree of frequency reuse. A significant challenge in implementing data networks at 60 GHz is the manufacture of low-cost RF transceivers capable of satisfying the system requirements. In order to produce transceivers that meet the additional demands of high-volume, mobility, and compactness, monolithic millimeter wave integrated circuits (MMICs) offer the most practical solution. In the design of radio tranceivers with a high degree of integration, the receiver front-end is typically the most critical component to overall system performance. High-performance low-noise amplifiers (LNAs) are now realizable at frequencies in excess of 100 GHz, and a wide variety of mixer topologies are available that are capable of downconversion from 60 GHz. However, local oscillators (LOs) capable of providing adequate output power at mm-wave frequencies remain bulky and expensive. There are several techniques that allow the use of a lower frequency microwave LO to achieve the same RF downconversion. One of these is to employ a subharmonic mixer. In this case, a lower frequency LO is applied and the RF mixes with a harmonic multiple of the LO signal to produce the desired intermediate frequency (IF). The work presented in this thesis will focus on the development of a GaAs MMIC 4-X subharmonic mixer in Finite Ground Coplanar (FGC) technology for operation at 60 GHz. The mixer topology is based on an antiparallel Schottky diode pair. A discussion of the mechanisms behind the operation of this circuit and the methods of practical implementation is presented. The FGC transmission lines and passive tuning structures used in mixer implementation are characterized with full-wave electromagnetic simulation software and 2-port vector network analyzer measurements. A characterization of mixer performance is obtained through simulations and measurement. The viability of this circuit as an alternative to other high-frequency downconversion schemes is discussed. The performance of the actual fabricated MMIC is presented and compared to currently available 60 GHz mixers. One particular MMIC design exhibits an 11.3 dB conversion loss at an RF of 58.5 GHz, an LO frequency of 14.0 GHz, and an IF of 2.5 GHz. This represents excellent performance for a 4X Schottky diode mixer at these frequencies. Finally, recommendations toward future research directions in this area are made. / Master of Science

Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d’entretien de type Colpitts,la mise en forme et jusqu’à l’adaptation du signal à sa charge d’utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s’orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del’architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l’avons reportée par flip chip sur une interfacespécifique pour / The increasing demand for high-performance devices featuring compact, lighter-weight designs with low-power consumptionalso impacts quartz crystal oscillators used in metrological applications (time bases, sensors), telephony or navigation. Inthis context, we have developed an ASIC (Application Specific Integrated Circuit) in 0.35 μm SiGe BiCMOS technology(Austriamicrosystems®) supplied by 3.3 V (±10%) to realize a miniaturized quartz crystal oscillator operating in the 10 MHzto 100 MHz frequency range. The fabricated die hosts several RF cells in a 4 mm2 area, including a sustaining amplifier(Colpitts topology), a signal shaping circuit and an output buffer dedicated to a specific load (50 W or HCMOS). These cellsare biased by a fully integrated CMOS bandgap voltage reference. The die power consumption remains lower than 100 mWfor a targeted phase noise floor as low as −150 dBc/Hz at a 40 MHz carrier frequency. A thermal control loop has in additionbeen partially integrated to the ASIC, in order to reduce the quartz resonator thermal sensitivity as well as to extend thepotential application field of the developed die to oven applications (OCXO). The thermal control, that is strongly dependanton the mechanical design, has been designed and tested by using electrical analogy modeling on Spectre® simulator. Finallyour integrated circuit has been connected to a specific substrate using flip chip technology to realize a miniaturized quartzcrystal oscillator packaged on a TO-8 enclosure (Ø15.2 mm).

Cette thèse porte sur le développement d'un capteur de pixel monolithique CMOS utilisé pourl’identification et le comptage des particules ionisés dan l’espace avec un flux élevé. Un nouveauconcept pour l’identification de l’espèce des particules proposé dans la présente étude, est basésur l'analyse des amas de particules déclenchés. Pour valider ce nouveau concept, un capteur detaille complet, qui comprend la matrice de pixel sensible aux particules ionisés signal, une chaînede traitement du signal analogique, un convertisseur analogue numérique de 3 bits, et untraitement du signal numérique a été conçu dans un processus de 0.35 μm. Le capteur sortiedirectement des informations de flux à travers 4 canaux avec un débit de données très faible(80 bps) et dissipation d’énergie minimale (~ 100 mW). Chaque canal représente particules avecdifférentes espèces et les énergies. La densité maximum de flux mesurable est jusqu'à 108particules/cm2/s (coups s'accumulent < 5%). Un prototype à échelle réduite a été fabriqué et testéavec trois types d'illumination de rayonnement (rayons X, les électrons et laser infrarouge). Tousles résultats obtenus valident le nouveau concept proposé. Un moniteur de rayonnement spatialtrès miniaturisé basé sur un capteur de pixel CMOS peut être prévu. Le moniteur peut présente lesmêmes performances que les compteurs actuels, mais avec une dissipation de puissance réduited'un ordre de grandeur qu'un poids, un volume d'encombrement et un coût moindre. En outre, enraison de ses sorties de haut niveau et faible débit de données, aucune traitement supplémentairedu signal dehors du capteur est nécessaire, ce qui le rend particulièrement attrayant pour desapplications dan les petits satellitaires. / This thesis focuses on the development of a CMOS monolithic pixel sensor used for space ionizingparticles identification and counting in high flux. A new concept for single particle identification isproposed in this study, which is based on the analysis of particle triggered clusters. To validate thisnew concept, a full size sensor including the sensitive pixel matrix, an analogue signal processingchain, a 3-bit analogue to digital converter, and a digital processing stage was designed in a 0.35μm process. The sensor directly output particles flux information through 4 channels with a verylow data rate (80 bps) and minimal power dissipation (~ 100mW). Each channel representsparticles with different species and energies. The highest measurable flux density is up to 108particles/cm2/s (hits pile up < 5%). A reduced scale prototype was fabricated and tested with 3types of radiation illumination (X-ray, electrons and infrared laser). All the results obtained validatethe proposed new concept and a highly miniaturized space radiation monitor based on a singleCMOS pixel sensor could be foreseen. The monitor could provide measurements of comparable orbetter quality than existing instruments, but at around an order of magnitude lower powerconsumption, mass and volume and a lower unit cost. Moreover, due to its high level and low datarate outputs, no signal treatment power aside the sensor is required which makes it especiallyattractive for small satellite application.

With continuous and aggressive scaling in semiconductor technology, there is an increasing gap between design expectation and manufactured silicon data. Research on DFM (Design for manufacturability), MFD (Manufacturing for Design) and statistical analysis have been investigated in recent years to bridge design and manufacturing. Fundamentally, layout is the final output from the design side and the input to the manufacturing side. It is also the last chance to dramatically modify the design efficiently and economically. In this dissertation, I present the modeling and optimization work on bridging the gap between design expectation and reality, improving performance and enhancing manufacturing yield. I investigate several stages of semiconductor design development including manufacturing process, device, interconnect, and circuit level. In the manufacturing process stage, a novel inverse lithography technology (ILT) is proposed for sub-wavelength lithography resolution enhancement. New intuitive transformations enable the method to gradually converge to the optimal solution. A highly efficient method for gradient calculation is derived based on partially coherent optical models. Dose variation is considered within the ILO process with the min-max optimization method and the computation overhead on dose process variation could be omitted. The methods are implemented in state-of-the-art industrial 32nm lithography environment. After the work in the lithography process stage provides both mask optimization and post-layout silicon image simulation, my work on the first non-rectangular device modeling card extends the post-layout lithography to post-litho electrical calibration. Based on the lithography simulation results, the non-rectangular gate shapes are extracted and their effect is investigated by the proposed non-rectangular device modeling card and post-litho circuit simulation flow. This work is not only the first non-rectangular device modeling card but also compatible with industry standard device models and the parameter extraction flow. Interconnect plays a more critical role in the nanometer scale IC design especially because of its impact on delay. The scattering effect that occurs in nanoscale wires is modeled and different methods of wire sizing/shaping are discussed. Based on closed-form resistivity model for nanometer scale Cu interconnect, new interconnect delay model and wire sizing/shaping strategies are developed. Based on the advanced modeling of process, device and interconnect, circuit level investigation is focused on statistical timing analysis with a new latch delay model. For the first time, both combinational logic and clock distribution circuits are integrated together through statistical timing of latch outputs. This dissertation studies the new phenomena of nanometer scale IC design and manufacture. Starting from the designed layout, through modeling, optimization and simulation, the work moves ahead to the mask pattern and silicon image, calibrates electrical properties of devices as well as circuits. Through above process, we can better connect layout with silicon data to reach design and manufacturing closure. / text

Major challenges in maintaining quality and reliability in today’s microelectronics devices come from the ever increasing level of integration in the device fabrication, as well as the high level of current densities that are carried through the microchip during operation. In order to have a framework for design and reliability assessment, it is imperative to develop a predictive capability for the thermal response of micro-electronic components. A computationally efficient and accurate multi-scale transient thermal methodology was developed using a combination of two different approaches: “Progressive Zoom-in” method and “Proper Orthogonal Decomposition (POD)” technique. The proposed technique has the capability of handling several decades of length scale from tens of millimeter at “package” level to several nanometers at “interconnects” level at a considerably lower computational cost, while maintaining satisfactory accuracy. This ability also applies for time scales from seconds to microseconds corresponding to various transient thermal events. The proposed method also provides the ability to rapidly predict thermal responses under different power input patterns, based on only a few representative detailed simulations, without compromising the desired spatial and temporal resolutions. It is demonstrated that utilizing the proposed model, the computational time is reduced by at least two orders of magnitude at every step of modeling. Additionally, a novel experimental platform was developed to evaluate rapid transient Joule heating in embedded nanoscale metallic films representing buried on-chip interconnects that are not directly accessible. Utilizing the state-of-the-art sub-micron embedded resistance thermometry the effect of rapid transient power input profiles with different amplitudes and frequencies were studied. It is also demonstrated that a spatial resolution of 6 µm and thermal time constant of below 1 µs can be achieved using this technique. Ultimately, the size effects on the thermal and material properties of embedded metallic films were studied. A state-of-the-art technique to extract thermal conductivity of embedded nanoscale interconnects was developed. The proposed structure is the first device that has enabled the conductivity measurement of embedded metallic films on a substrate. It accounts for the effect of the substrate and interface without compromising the sensitivity of the device to the thermal conductivity of the metallic film. Another advantage of the proposed technique is that it can be integrated within the structure and be used for measurements of embedded or buried structures such as nanoscale on chip interconnects, without requiring extensive micro-fabrication. The dependence of the thermal conductivity on temperature was also investigated. The experimentally measured values for thermal conductivity and its dependence on temperature agree well with previous studies on free-standing nanoscale metallic bridges.

Depuis ces dernières années, les composants fortement submicroniques du commerce sont utilisés dans les équipements aéronautiques pour des applications spécifiées pour durer plusieurs décennies. Toutefois, ces composants sont destinés aux marchés de masse que représentent les secteurs de la micro informatique et des télécommunications et ne sont pas spécifiques au marché aéronautique. De ce fait, ces composants sont spécialement conçus pour des besoins dits de haute performance ou de basse consommation et pour lesquels la fiabilité n’est pas un critère prioritaire. Pour satisfaire ces marchés, une nouvelle génération technologique émerge tous les deux ans en imposant à chaque fois, une diminution des dimensions des métallisations BEOL ainsi que des transistors FEOL et/ou l’introduction de nouveaux matériaux. Ces modifications ont conduit à une aggravation des mécanismes de défaillance par usure pour les générations de composants fortement submicroniques, au point de ne plus satisfaire les spécifications en durée de vie des équipements aéronautiques. Cette étude s’attache donc à montrer l’impact que peuvent avoir la réduction des dimensions ainsi que la nature des matériaux, sur la durée de vie des technologies numériques CMOS 500 à 45 nm. Pour cela, les mécanismes de défaillances du circuit intégré ont été modélisés et étudiés au travers de trois applications aéronautiques. En complément, des tests de vieillissement de type HCI et NBTI pratiqués sur une SRAM de génération 90 nm ont permis de valider les prédictions. Enfin, les travaux aboutissent à une méthodologie de sélection de composants fortement submicroniques pour une application spécifique, en fonction de la technologie. / For some years, deep sub micron components have been used in aeronautic equipment for long term applications (generally few decades). However, these components are devoted to mass markets that are basically microcomputers and telecommunications and not especially to aeronautics. Hence, deep sub micron components are manufactured for high performance and low consumption needs and unfortunally, reliability is not the main concern. In order to supply these markets, a new generation of components generally arise every two years, introducing BEOL and FEOL scaling and/or new materials. As a consequence, these improvements have induced a lifetime degradation of devices that can threaten their use for longtime specifications of aeronautic equipement. This study points out the effects of scaling and material improvements on the lifetime degradation of CMOS integrated cicuits between the nodes 500-45 nm. To do so, silicon failure mechanisms have been modelised and investigated on three aeronautic applications. As a complement, some HCI and NBTI lifetests have been performed on 90 nm SRAM in order to validate previous lifetime predictions. Finally, this work leads to a methodology for the selection of deep sub micron components for a specific use, depending on the technology.

La pénétration importante d’objets communicants dans notre vie quotidienne révèle des défis important quant à leur développement. Notamment l’explosion d'applications multimédia sans fil pour l'électronique grand public fait de la consommation électrique une métrique clef dans la conception des dispositifs portables multimodes sans fil. Les émetteurs-récepteurs conventionnels proposent des performances fixes et sont conçus pour respecter ces hautes performances dans toutes les conditions de communication sans fil. Cependant, la plupart du temps, le canal n'est pas dans le pire cas de communication et ces émetteurs-récepteurs sont donc surdimensionnés. En connaissant l’état du canal en temps réel, de tels dispositifs pourraient s'adapter aux besoins et réduire significativement leur consommation électrique. Le défi consiste à respecter la Qualité de Service , ou Quality of Service (QoS) en anglais, imposée par les différents standards de communication. Afin de rester compétitifs, les émetteurs-récepteurs adaptatifs doivent donc proposer une même QoS que ceux déjà disponibles sur le marché. Ainsi, ni la portée de communication ni le temps de réponse ne peuvent être dégradés.Basé sur ces exigences, cette thèse propose une technique d'adaptation pour la conception d'un récepteur reconfigurable qui fonctionne à la limite des performances nécessaires pour recevoir le signal utile. Ainsi, le récepteur proposé est toujours au minimum de consommation électrique tout en garantissant la bonne QoS. Ceci permet alors de multiplier la durée de vie de sa batterie par un facteur 5.Cette adaptabilité est démontrée ensuite côté circuit par la conception d'un LNA (Amplificateur Faible Bruit) dont les performances sont reconfigurables. En effet, en tant que premier élément de la chaîne de réception, le LNA limite le récepteur en termes de sensibilité. Ces travaux exploitent la technologie FD-SOI (Fully Depleted Silicon-On-Insulator) pour d’une part, réduire la consommation du LNA et d’autre part, ajouter de la reconfigurabilité à ce même circuit. / Communicating objects are inviting themselves into daily life leading to digitization of the physical world. This explosion of multimedia wireless applications for consumer electronics makes the power consumption a key metric in the design of multi-mode wireless portable devices. Conventional transceivers have fixed performances and are designed to meet high performances in all wireless link conditions. However, most of the time, the channel of communication is not at worst case and these transceivers are therefore over specified. Being aware of the channel link conditions would allow such devices to adapt themselves and to reduce significantly their power consumption. Therefore, the challenge is to propose a QoS (Quality of Service) in terms of communication range, response time as instance, equivalent to industrial modules with a reduced overall power consumption.To address this purpose, this thesis proposes a design strategy for the implementation of adaptive radio-frequency receiver (Rx) modules. Hence the Rx front end achieves the correct QoS for various scenarii of communications with a minimum of power consumption.As a proof of concept, the adaptive approach is demonstrated with the design of a tunable LNA (Low Noise Amplifier). As the first element of the receiver chain, the LNA limits the receiver in terms of sensitivity and is therefore a good candidate to perform reconfiguration. The body biasing of the FD-SOI (Fully Depleted Silicon-On-Insulator) technology is first exploited to reduce the power consumption of a circuit and then as an opportunity to perform circuit tunability.