The ultimate goal of the modern wireless communication industry is the full integration of digital, analog, and radio frequency (RF) functions. The most successful solution for such demands has been complementary metal oxide semiconductor (CMOS) technology, thanks to its cost-effective material and great versatility. Power amplifier (PA), the biggest bottleneck to integrate in a single-chip transceiver in wireless communications, significantly influences overall system performance. Recent advanced wireless communication systems demand a power amplifier that can simultaneously support different communication standards. A fully integrated single-chip tunable CMOS power amplifier is the best solution in terms of the cost and level of integration with other functional blocks of an RF transceiver. This work, for the first time, proposes a fully integrated band-switchable RF power amplifier by using a novel approach towards switching the matching networks. In this approach, which is called Bit Optimized Reconfigurable Network (BORN), two matching networks which can be controlled by digital bits will provide three operating frequency bands for the power amplifier. In order to implementing the proposed BORN PA, a robust high-power RF switch is presented by using resistive body floating technique and 6-terminal triple-well NMOS. The proposed BORN PA delivers measured saturated output power (Psat) of 21.25/22.25/ 23.0dBm at 960MHz/1317MHz/1750MHz, respectively. Moreover, the proposed BORN PA provides respective 3-dB bandwidth of 400MHz/425MHz/550MHz, output 1-dB compression point (P1dB) of 19.5dBm/20.0dBm/21.0dBm, and power-added efficiency (PAE) of 9/11/13% at three targeted frequency bands, respectively. The promising results show that the proposed BORN PA can be a practical solution for RF multiband applications in terms of the cost and level of integration with other functional blocks of an RF transceiver.

Operational amplifier will be designed and optimized with respect to set of required parameters. Real CMOS technology (available at Department of Microelectronics) will be used for designed OTA circuit and its simulations. Designed OTA will be used as universal operation amplifier configurable block in FPAA (field-programmable analog array) structures.

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Microcontrollers and integrated circuits in general have become ubiquitous in the world today. All aspects of our lives depend on them from driving to work, to calling our friends, to checking our bank account balance. People who would do harm to individuals, corporations and nation states are aware of this and for that reason they seek to find or create and exploit vulnerabilities in integrated circuits. This dissertation contains three papers dealing with these types of vulnerabilities. The first paper talks about a vulnerability that was found on a microcontroller, which is a type of integrated circuit. The final two papers deal with hardware trojans. Hardware trojans are purposely added to the design of an integrated circuit in secret so that the manufacturer doesn’t know about it. They are used to damage the integrated circuit, leak confidential information, or in other ways alter the circuit. Hardware trojans are a major concern for anyone using integrated circuits because an attacker can alter a circuit in almost any way if they are successful in inserting one. A known method to prevent hardware trojan insertion is discussed and a type of circuit for which this method does not work is revealed. The discussion of hardware trojans is concluded with a new way to detect them before the integrated circuit is manufactured. Modern deep learning models are used to detect the portions of the hardware trojan called triggers that activate them.

As multistep, multilayer processing in semiconductor industry becomes more complex, the role of cleaning solutions and etching chemistries are becoming important in enhancing yield and in reducing defects. This thesis demonstrates successful formulations that exhibit copper and tungsten compatibility, and are capable of Inter Layer Dielectric (ILD) cleaning and selective Ti etching. The corrosion behavior of electrochemically deposited copper thin films in deareated and non-dearated cleaning solution containing hydrofluoric acid (HF) has been investigated. Potentiodynamic polarization experiments were carried out to determine active, active-passive, passive, and transpassive regions. Corrosion rates were calculated from tafel slopes. ICP-MS and potentiodynamic methods yielded comparable Cu dissolution rates. Interestingly, the presence of hydrogen peroxide in the cleaning solution led to more than an order of magnitude suppression of copper dissolution rate. We ascribe this phenomenon to the formation of interfacial CuO which dissolves at slower rate in dilute HF. A kinetic scheme involving cathodic reduction of oxygen and anodic oxidation of Cu0 and Cu+1 is proposed. It was determined that the reaction order kinetics is first order with respect to both HF and oxygen concentrations. The learnings from copper corrosion studies were leveraged to develop a wet etch/clean formulation for selective titanium etching. The introduction of titanium hard-mask (HM) for dual damascene patterning of copper interconnects created a unique application in selective wet etch chemistry. A formulation that addresses the selectivity requirements was not available and was developed during the course of this dissertation. This chemical formulation selectively strips Ti HM film and removes post plasma etch polymer/residue while suppressing the etch rate of tungsten, copper, silicon oxide, silicon carbide, silicon nitride, and carbon doped silicon oxide. Ti etching selectivity exceeding three orders of magnitude was realized. Surprisingly, it exploits the use of HF, a chemical well known for its SiO2 etching ability, along with a silicon precursor to protect SiO2. The ability to selectively etch the Ti HM without impacting key transistor/interconnect components has enabled advanced process technology nodes of today and beyond. This environmentally friendly formulation is now employed in production of advanced high-performance microprocessors and produced in a 3000 gallon reactor.

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京都大学 / 新制・課程博士 / 博士(情報学) / 甲第24748号 / 情博第836号 / 新制||情||140(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 湊 真一, 教授 橋本 昌宜, 教授 岡部 寿男 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

The demand for low-power A/D conversion techniques has motivated the exploration of charge-transfer amplifiers (CTAs) to construct efficient, precise voltage comparators. Despite notable advantages over classical, continuous-time architectures, little is understood about the dynamic behavior of CTAs or their utility in precision A/D converters. Accordingly, this dissertation presents several advancements related to the design and analysis of charge-transfer amplifiers for low-power data conversion. First, an analysis methodology is proposed which leads to a deterministic model of the voltage transfer function. The model is generalized to any timing scheme and can be extended to account for nonlinear threshold modulation. The model is compared with simulation results and test chip measurements, and shows good agreement over a broad range of circuit parameters. Three new charge-transfer amplifier architectures are proposed to address the limitations of existing designs: first, a truly differential CTA which improves upon the pseudo-differential configuration; second, a CTA which achieves more than 10x reduction in input capacitance with a moderate reduction in common mode range; third, a CTA which combines elements of the first two but also operates without a precharge voltage and achieves nearly rail to rail input range. Results from test chips fabricated in 0.6 um CMOS are described. Power dissipation in CTAs is considered and an idealized power consumption model is compared with measured test chip results. Four figures of merit (FOMs) are also proposed, incorporating power dissipation, active area, input charging energy and accuracy. The FOMs are used to compare the relative benefits and costs of particular charge-transfer amplifiers with respect to flash A/D converter applications. The first 10-bit CTA-based A/D converter is reported. It consumes low dynamic power of 600 uW/MSPS from a 2.1 V supply, 40% less than the current state of the art of 1 mW/MSPS. This subranging type converter incorporates capacitive interpolation to achieve a nearly ideal comparator count and power consumption. A distributed sample-and-hold (S/H) eliminates the need for a separate S/H amplifier. A test chip, fabricated in 0.6 um 2P/3M CMOS, occupies 2.7 mm2 and exhibits 8.2 effective bits at 2 MSPS.