Isotropically conductive adhesives (ICAs) are promising as a lead-free interconnect material; However, ICAs have a higher resistivity compared to tin/lead solder. The higher resistivity of ICAs results from the large contact resistance between conductive fillers. Several novel approaches to engineer the interface between electrically conductive fillers were studied to develop highly conductive ICAs. Shown in this dissertation are three methodologies to reduce contact resistance: low temperature sintering, fast sintering and in-situ reduction. Furthermore, two approaches, surface modification and in-situ protection, were developed to prevent oxidation and corrosion of silver-coated copper flakes to produce low cost ICAs. The findings and insights in this dissertation significantly contribute to (1) understanding of filler-filler, filler-polymer and structure-property relationships of ICAs; (2) the structural design and formulation of high performance ICAs; and (3) the wider use of ICAs in emerging applications such as printed electronics and solar cells.

The main objective of this research is to predict the wirelength, area, delay, and power of multi-granularity three-dimensional integrated circuits (3D ICs), to develop physical design methodologies and algorithms for the design of multi-granularity 3D ICs, and to investigate the impact of through-silicon vias (TSVs) on the quality of 3D ICs. This dissertation supports these objectives by addressing six research topics. The first pertains to analytical models that predict the interconnects of multi-granularity 3D ICs, and the second focuses on the development of analytical models of the capacitive coupling of TSVs. The third and the fourth topics present design methodologies and algorithms for the design of gate- and block-level 3D ICs, and the fifth topic pertains to the impact of TSVs on the quality of 3D ICs. The final topic addresses topography variation in 3D ICs. The first section of this dissertation presents TSV-aware interconnect prediction models for multi-granularity 3D ICs. As previous interconnect prediction models for 3D ICs did not take TSV area into account, they were not capable of predicting many important characteristics of 3D ICs related to TSVs. This section will present several previous interconnect prediction models that have been improved so that the area occupied by TSVs is taken into account. The new models show numerous important predictions such as the existence of the number of TSVs minimizing wirelength. The second section presents fast estimation of capacitive coupling of TSVs and wires. Since TSV-to-TSV and TSV-to-wire coupling capacitance is dependent on their relative locations, fast estimation of the coupling capacitance of a TSV is essential for the timing optimization of 3D ICs. Simulation results show that the analytical models presented in this section are sufficiently accurate for use at various design steps that require the computation of TSV capacitance. The third and fourth sections present design methodologies and algorithms for gate- and block-level 3D ICs. One of the biggest differences in the design of 2D and 3D ICs is that the latter requires TSV insertion. Since no widely-accepted design methodology designates when, where, and how TSVs are inserted, this work develops and presents several design methodologies for gate- and block-level 3D ICs and physical design algorithms supporting them. Simulation results based on GDSII-level layouts validate the design methodologies and present evidence of their effectiveness. The fifth section explores the impact of TSVs on the quality of 3D ICs. As TSVs become smaller, devices are shrinking, too. Since the relative size of TSVs and devices is more critical to the quality of 3D ICs than the absolute size of TSVs and devices, TSVs and devices should be taken into account in the study of the impact of TSVs on the quality of 3D ICs. In this section, current and future TSVs and devices are combined to produce 3D IC layouts and the impact of TSVs on the quality of 3D ICs is investigated. The final section investigates topography variation in 3D ICs. Since landing pads fabricated in the bottommost metal layer are attached to TSVs, they are larger than TSVs, so they could result in serious topography variation. Therefore, topography variation, especially in the bottommost metal layer, is investigated and two layout optimization techniques are applied to a global placement algorithm that minimizes the topography variation of the bottommost metal layer of 3D ICs.

In this thesis, the circuits which comprise the front-end of a millimeter-wave transmit-receive module are investigated using a state-of-the-art 90 nm SiGe BiCMOS process for use in radar remote sensing applications. In Chapter I, the motivation for a millimeter-wave radar in the context of space-based remote sensing is discussed. In addition, an overview of Silicon-germanium technology is presented, and the chapter concludes with a discussion of design challenges at millimeter-wave frequencies. In Chapter II, a brief history of radar technology is presented - the motivations leading to the development of the transmit-receive module for active electronically scanned arrays are discussed, and the critical components which reside in nearly every high-frequency transmit-receive module are introduced. In Chapter III, the design and results of a W-band single-pole, double-throw switch using SiGe p-i-n diodes are discussed. In particular, the design topology and methods used to achieve low-loss and high power handling over a wide matching bandwidth without sacrificing isolation are described. In Chapter IV, the design and results of a W-band low-noise amplifier using SiGe HBT's are discussed. The design methodologies used to achieve high gain and exceptional noise performance over a wide matching bandwidth are described. Concluding remarks and a discussion of future work are in Chapter V.

Conventional solder balls used in microelectronic packaging suffer from thermo- mechanical damage due to difference in coefficient of thermal expansion between the die and the substrate or the substrate and the board. Compliant interconnects are replacements for solder balls which accommodate this differential displacement by mechanically decoupling the die from the substrate or the substrate from the board and aim to improve overall reliability and life of the microelectronic component. Research is being conducted to develop compliant interconnect structures which offer good mechanical compliance without adversely affecting electrical performance, thus obtaining good thermo-mechanical reliability. However, little information is available regarding the behavior of compliant interconnects under shock and impact loads. The objective of this thesis is to study the response of a proposed multi-path compliant interconnect structure when subjected to shock and impact loading. As part of this work, scaled-up substrate-compliant interconnect-die assemblies will be fabricated through stereolithography techniques. These scaled-up prototypes will be subjected to experimental drop testing. Accelerometers will be placed on the board, and strain gauges will be attached to the board and the die at various locations. The samples will be dropped from different heights to different shock levels in the components, according to Joint Electron Devices Engineering Council (JEDEC) standards. In parallel to such experiments with compliant interconnects, similar experiments with scaled-up solder bump interconnects will also be conducted. The strain and acceleration response of the compliant interconnect assemblies will be compared against the results from solder bump interconnects. Simulations will also be carried out to mimic the experimental conditions and to gain a better understanding of the overall response of the compliant interconnects under shock and impact loading. The findings from this study will be helpful for improving the reliability of compliant interconnects under dynamic mechanical loading.

As the volume of data processed by computers and telecommunication devices rapidly increases, high speed serial link has been challenged to maximize its I/O bandwidth with limited resources of channels and semiconductor devices. This trend requires designers’ relentless effort for innovations. The innovations are required not only at system level but also at sub-system and circuit level. This dissertation discusses two important topics regarding high speed serial links: Clock and Data Recovery (CDR) and Current Mode Logic (CML). This dissertation proposes a mixed-mode adaptive loop gain Bang-Bang CDR. The proposed CDR enhances jitter performances even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of the Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode-based Charge Pump (CP) is proposed to minimize CP latency. The effectiveness of the proposed techniques was experimentally demonstrated by various jitter performance tests. This dissertation also presents a process-variation-resilient CML. A typical CML requires over-design to meet the specification over the wide range of process parameter variations. To address this issue, the proposed CML employs a time-reference-based adaptive biasing chain with replica load. It adjusts a variable load resistor to simultaneously regulate time-constant, voltage swing, level-shifting and DC gain. The performance of the high speed building blocks such as Bang-Bang Phase Detectors, frequency dividers and PRBS generators can be more accurately regulated with the proposed CML approach. The prototype is fabricated to experimentally compare the process-variation-induced performance degradation between the conventional and the proposed CML. Compared to the conventional CML, the proposed architecture significantly reduces the performance degradation on divider self-oscillation frequency, PRBS generator speed and PRBS output jitters over the process-variation with only <3% additional power dissipation.

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law at IC level and system miniaturization with System-On-Package (SOP) paradigm at system level, have resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. However, system miniaturization poses several electrical and thermal challenges that demand innovative solutions including advanced materials, bonding and assembly techniques. Heterogeneous material and device integration for thermal structures and IC assembly are limited by the bonding technology and the electrical and thermal impedance of the bonding interfaces. Solder - based bonding technology that is prevalent today is a major limitation to future systems. The trend towards miniaturized systems is expected to drive downscaling of IC I/O pad pitches from 40µm to 1- 5µm in future. Solder technology imposes several pitch, processability and cost restrictions at such fine pitches. Furthermore, according to International Technology Roadmap for Semiconductors (ITRS-2006), the supply current in high performance microprocessors is expected to increase to 220 A by 2012. At such supply current, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer sized technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Similarly, thermal power dissipation is growing to unprecedented high with a projected power of 198 W by 2008 (ITRS 2006). Present thermal interfaces are not adequate for such high heat dissipation. Recently, copper based thin film bonding has become a promising approach to address the abovementioned challenges. However, copper-copper direct bonding without using solders has not been studied thoroughly. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. Hence, there is a need to develop a novel low temperature copper to copper bonding process. In the present study, nanomaterials - based copper-to-copper bonding is explored and developed as an alternative to solder-based bonding. To demonstrate fine pitch bonding, the patterning of these nanoparticles is crucial. Therefore, two novel self-patterning techniques based on: 1.) Selective wetting and 2.) Selective nanoparticle deposition, are developed to address this challenge. Nanoparticle active layer facilitates diffusion and, thus, a reliable bond can be achieved using less thermal budget. Quantitative characterization of the bonding revealed good metallurgical bonding with very high bond strength. This has been confirmed by several morphological and structural characterizations. A 30-micron pitch IC assembly test vehicle is used to demonstrate fine pitch patternability and bonding. In conclusion, novel nanoparticle synthesis and patterning techniques were developed and demonstrated for low-impedance and low-cost electrical and thermal interfaces.

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.

The objective of this research work is to develop an efficient methodology for chip-package cosimulation. In the traditional design flow, the integrated circuit (IC) is first designed followed by the package design. The disadvantage of the conventional sequential design flow is that if there are problems with signal and power integrity after the integration of the IC and the package, it is expensive and time consuming to go back and change the IC layout for a different input/output (IO) pad assignment. To overcome this limitation, a concurrent design flow, where both the IC and the package are designed together, has been recommended by researchers to obtain a fast design closure. The techniques from this research work will enable multiscale cosimulation of the chip and the package making the concurrent design flow paradigm possible. Traditional time-domain techniques, such as the finite-difference time-domain method, are limited by the Courant condition and are not suitable for chip-package cosimulation. The Courant condition gives an upper bound on the time step that can be used to obtain stable simulation results. The smaller the mesh dimension the smaller is the Courant time step. In the case of chip-package cosimulation the on-chip structures require a fine mesh, which can make the time step prohibitively small. An unconditionally stable scheme using Laguerre polynomials has been recommended for chip-package cosimulation. Prior limitations in this method have been overcome in this research work. The enhanced transient simulation scheme using Laguerre polynomials has been named SLeEC, which stands for simulation using Laguerre equivalent circuit. A full-wave EM simulator has been developed using the SLeEC methodology. A scheme for efficient use of full-wave solver for chip-package cosimulation has been proposed. Simulation of the entire chip-package structure using a full-wave solver could be a memory and time-intensive operation. A more efficient way is to separate the chip-package structure into the chip, the package signal-delivery network, and the package power-delivery network; use a full-wave solver to simulate each of these smaller subblocks and integrate them together in the following step, before a final simulation is done on the integrated network. Examples have been presented that illustrate the technique.

The current trend of ever larger clusters and data centers has coincided with a dramatic increase in the cost and power of these installations. While many efficiency improvements have focused on processor power and cooling costs, reducing the cost and power consumption of high-performance memory has mostly been overlooked. This thesis proposes a new address translation model called Dynamic Partitioned Global Address Space (DPGAS) that extends the ideas of NUMA and software-based approaches to create a high-performance hardware model that can be used to reduce the overall cost and power of memory in larger server installations. A memory model and hardware implementation of DPGAS is developed, and simulations of memory-intensive workloads are used to show potential cost and power reductions when DPGAS is integrated into a server environment.

The goal of this research was to develop new experimental techniques to quantitatively study the interfacial fracture of micro-contact thin film interconnects used in microelectronic applications under monotonic and cyclic loadings. The micro-contact spring is a new technology that is based on physical vapor deposited thin film cantilevers with a purposely-imposed stress gradient through the thickness of the film. These "springs" have the promise of being the solution to address near-term wafer level probing and long-term high-density chip-to-next level microelectronic packaging challenges, as outlined by the International Technology Roadmap for Semiconductors. The success of this technology is, in part, dependent on the ability to understand the failure mechanism under monotonic and cyclic loadings. This research proposes two experimental methods to understand the interfacial fracture under such monotonic and fatigue loading conditions. To understand interfacial fracture under monotonic loading, a fixtureless superlayer-based delamination test has been developed. Using stress-engineered Cr layer and a release layer with varying width, this test can be used to measure interfacial fracture toughness under a wide range of mode mixity. This test uses common IC fabrication techniques and overcomes the shortcomings of available methods. The developed test has been used to measure the interfacial fracture toughness for Ti/Si interface. It was found that for low mode mixity Ti/Si thin film interfaces, the fracture toughness approaches the work of adhesion which is essentially the Ti-Si bond energy for a given bond density. In addition to the monotonic decohesion test, a fixtureless fatigue test is developed to investigate the interfacial crack propagation. Using a ferromagnetic material deposited on the micro-contact spring, this test employs an external magnetic field to be able to drive the interfacial crack. Fatigue crack growth can be monitored by E-beam lithography patterned metal traces that are 10 to 40nm wide and 1 to a few µm in spacing. The crack initiation and propagation can be monitored through electrical resistance measurement. In the conducted experiments, it is seen that the interfacial delamination does not occur under fatigue loading, and that the micro-contact springs are robust against interfacial fracture for probing and packaging applications.