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This dissertation describes the fabrication and integration of a thin film edge emitting laser (EEL) whose optical output is coupled into a polymer waveguide integrated onto the same electrical interconnection substrate. This embedded laser/waveguide structure is a fundamental building block toward the realization of planar lightwave circuits using embedded optical interconnections. The demonstration of a thin film laser integrated with a planar waveguide eliminates the need for either an external optical source coupled to the waveguide or a bump bonded optical source with a beam turning element to turn an optical beam into the waveguide. In this work, the wedge-induced facet cleaving (WFC) method is adapted to fabricate the thin film EELs. Bisbenzocyclobutene (BCB) polymers are used to fabricate channel waveguides, and thin film lasers are integrated with the polymer waveguides. The coupling efficiency from the laser to the polymer waveguide is estimated through measurement and theoretically calculated. In the theoretical calculation, the thin film transfer matrix method is used to analyze the optical modes in the semiconductor cavity. The coupling efficiency from the laser to the polymer waveguide is analyzed using a finite element method (FEM), and are then compared to the experimental results. The experimentally estimated coupling efficiency is in good agreement with that of the theoretical calculation. In addition, the relationship between threshold current, output power, and facet reflectivity of the thin film laser is analyzed using FEM.

The trend to high I/O density, performance and miniaturization at low cost is driving the industry towards shrinking interposer design rules, requiring a new set of packaging technologies. Low-CTE packages from silicon, glass and low-CTE organic substrates enable high interconnection density, high reliability and integration of system components. However, the large CTE mismatch between the package and the board presents reliability challenges for the board-level interconnections. Novel stress-relief structures that can meet reliability requirements along with electrical performance while meeting the cost constraints are needed to address these challenges. This thesis focuses on a comprehensive methodology starting with modeling, design, fabrication and characterization to validate such stress-relief structures. This study specifically explores SMT-compatible stress-relief microwire arrays in thin polymer carriers as a unique and low-cost solution for reliable board-level interconnections between large low-CTE packages and printed wiring boards. The microwire arrays are pre-fabricated in ultra-thin carriers using low-cost manufacturing processes such as laser vias and copper electroplating, which are then assembled in between the interposer and printed wiring board (PWB) as stress-relief interlayers. The microwire array results in dramatic reduction in solder stresses and strains, even with larger interposer sizes (20 mm × 20 mm), at finer pitch (400 microns), without the need for underfill. The parallel wire arrays result in low resistance and inductance, and therefore do not degrade the electrical performance. The scalability of the structures and the unique processes, from micro to nanowires, provides extendibility to finer pitch and larger package sizes. Finite element method (FEM) was used to study the reliability of the interconnections to provide guidelines for the test vehicle design. The models were built in 2.5D geometries to study the reliability of 400 µm-pitch interconnections with a 100 µm thick, 20 mm × 20 mm silicon package that was SMT-assembled onto an organic printed wiring board. The performance of the microwire array interconnection is compared to that of ball grid array (BGA) interconnections, in warpage, equivalent plastic strain and projected fatigue life. A unique set of materials and processes was used to demonstrate the low-cost fabrication of microwire arrays. Copper microwires with 12 µm diameter and 50 µm height were fabricated on both sides of a 50 µm thick, thermoplastic polymer carrier using dryfilm based photolithography and bottom-up electrolytic plating. The copper microwire interconnections were assembled between silicon interposer and FR-4 PWB through SMT-compatible process. Thermal mechanical reliability of the interconnections was characterized by thermal cycling test from -40°C to 125°C. The initial fatigue failure in the interconnections was identified at 700 cycles in the solder on the silicon package side, which is consistent with the modeling results. This study therefore demonstrated a highly-reliable and SMT-compatible solution for board-level interconnections between large low-CTE packages and printed wiring board.

<p>The accelerating growth of e-business and technologies has raised the interest in transforming traditional business models or developing new ones. Most of the e-business model research has been devoted to giving taxonomies of e-business models. Though defining e-business model and decomposing it into atomic elements traditionally has been a task for researchers, the concepts surrounding them have been subject to debate lately. While there is an extensive research conducted towards identifying and analyzing key components in e-business models, limited research has been noted in identifying component values or factors and the interconnections between components. In this thesis we review the e-business models literature using literature study in order to give an overview of e-business model definitions, identify the component values and interconnections between components and finally a framework provided that shows all these components, values and interconnections.</p>

The accelerating growth of e-business and technologies has raised the interest in transforming traditional business models or developing new ones. Most of the e-business model research has been devoted to giving taxonomies of e-business models. Though defining e-business model and decomposing it into atomic elements traditionally has been a task for researchers, the concepts surrounding them have been subject to debate lately. While there is an extensive research conducted towards identifying and analyzing key components in e-business models, limited research has been noted in identifying component values or factors and the interconnections between components. In this thesis we review the e-business models literature using literature study in order to give an overview of e-business model definitions, identify the component values and interconnections between components and finally a framework provided that shows all these components, values and interconnections.

Large scale data centers (DC) and high performance computing (HPC) systems require more and more computing power at higher energy efficiency. They are already consuming megawatts of power, and a linear extrapolation of trends reveals that they may eventually lead to unrealistic power consumption scenarios in order to satisfy future requirements (e.g., Exascale computing). Conventional complementary metal oxide semiconductor (CMOS)-based electronic interconnects are not expected to keep up with the envisioned future board-to-board and chip-to-chip (within multi-chip-modules) interconnect requirements because of bandwidth-density and power-consumption limitations. However, low-power and high-speed optics-based interconnects are emerging as alternatives for DC and HPC communications; they offer unique opportunities for continued energy-efficiency and bandwidth-density improvements, although cost is a challenge at the shortest length scales. Plasmonics-based interconnects on the other hand, due to their extremely small size, offer another interesting solution for further scaling operational speed and energy efficiency. At the device-level, CMOS compatibility is also an important issue, since ultimately photonics or plasmonics will have to be co-integrated with electronics. In this paper, we survey the available literature and compare the aforementioned interconnect technologies, with respect to their suitability for high-speed and energy-efficient on-chip and offchip communications. This paper refers to relatively short links with potential applications in the following interconnect distance hierarchy: local group of racks, board to board, module to module, chip to chip, and on chip connections. We compare different interconnect device modules, including low-energy output devices (such as lasers, modulators, and LEDs), photodetectors, passive devices (i.e., waveguides and couplers) and electrical circuitry (such as laserdiode drivers, modulator drivers, transimpedance, and limiting amplifiers). We show that photonic technologies have the potential to meet the requirements for selected HPC and DC applications in a shorter term. We also present that plasmonic interconnect modules could offer ultra-compact active areas, leading to high integration bandwidth densities, and low device capacitances allowing for ultra-high bandwidth operation that would satisfy the application requirements further into the future.

Effective power delivery in Double-sided 3-D glass interposer packages was proposed, investigated, and demonstrated towards achieving high logic-to-memory bandwidth. Such 3-D interposers enable a simpler alternative to direct 3-D stacking by providing low-loss, wide-I/O channels between the logic device on one side of the ultra-thin glass interposer and memory stack on the other side, eliminating the need for complex TSVs in the logic die. A simplified PDN design approach with power-ground planes was proposed to overcome resonance challenges from (a) added parasitic inductance in the lateral power delivery path from the printed wiring board (PWB), due to die placement on the bottom side of the interposer, and (b) the low-loss property of the glass substrate. Based on this approach, this dissertation developed three important suppression solutions using, (a) the 3-D interposer package configuration, (b) the selection of embedded and SMT-based decoupling capacitors, and (c) coaxial power-ground planes with TPVs. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board (PWB) and chip-level models. Two-metal and four-metal layer test vehicles were fabricated on 30-μm and 100-μm thick glass substrates using a panel-based double-side fabrication process, for potential lower cost and improved electrical performance. The PDN test structures were characterized upto 20 GHz, to demonstrate the measured verification of (a) 3-D glass interposer power delivery network and (b) resonance suppression. The data and analysis presented in this dissertation prove that the objectives of this research were met successfully, leading to the first demonstration of effective PDN design in ultra-thin (30-100μm), and 3-D double-sided glass BGA packages, by suppressing the PDN noise from mode resonances.

Mémoire numérisé par la Division de la gestion de documents et des archives de l'Université de Montréal.

Este trabalho tem como objetivo estudar e propor métodos de teste funcional visando a detecção e localização de falhas na infra-estrutura das redes-em-chip. Para isso, o trabalho apresenta, inicialmente, uma descrição das principais características das redes-em-chip, explicando o que elas são e para que elas servem. Em seguida são apresentados conceitos de teste de circuitos integrados, bem como trabalhos relacionados ao teste das redes-em-chip. Um método de teste visando a detecção de falhas nas interconexões de dados de uma NoC é apresentado no trabalho, sendo este método posteriormente estendido para incluir as interconexões de controle. Os circuitos de teste necessários para implementar a estratégia de teste proposta também são descritos. A partir do método de teste apresentado, é feito um estudo sobre sua capacidade de localização de falhas, onde alterações visando o aumento dessa capacidade de localização de falhas são propostas. Por fim o método de teste é estendido para detecção de falhas nos roteadores da rede. / The purpose of this work is to study and propose functional test methods that aim the detection and location of faults in the NoC’s infrastructure. In order to do so, this work presents, initially, a description of the main characteristics of networks-on-chip, explaining what are NoCs and what is their purpose. Fallowing this description, some concepts related to the test of integrated circuits are presented as well as related works on NoC testing. A method aiming the detection of data interconnect faults in a NoC is presented in this work. This method is later extended to include faults in the control interconnections as well. The circuits used to implement the proposed strategy are also described here. Based on the proposed test strategy, the method’s capability to locate faults is studied. Changes are proposed to the test method in order to increase this fault location capability. Finally, the test method is extended to include faults inside the router’s logic.

Microelectronic interconnections require advanced joining techniques. Direct metal bonding methods, which include thercomsonic and thermocompression bonding, offer remarkable advantages over soldering and adhesives joining. These processes are reviewed in this paper. The progress made in this area is outlined. Some work concerned with the bonding modeling is also presented. This model is based on the joint interface mechanics resulting from compression. Both bump and substrate deformation are taken into account. The improved understanding of the relationship between the deformation and bonding formation may provide more accurate joint evaluation criterion. / Singapore-MIT Alliance (SMA)