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The doctoral thesis deals with development and design of novel architectures of digital filters for low-power integrated circuits. The main goal was to achieve optimum parameters of digital filters with respect to the chip area, power consumption and operating frequency. The target group of the proposed architectures are application specific integrated circuits designed for signal processing from sensors using delta-sigma modulators. Three novel architectures of digital filters optimized for low-power integrated circuits are presented in the thesis. The thesis provides analysis and comparison of parameters of the new filter architectures with the parameters of architectures generated by Matlab tool. A software tool has been designed and developed for the practical application of the proposed architectures of digital filters. The developed software tool allows generating hardware description of the filters with respect to defined parameters.

Les travaux de cette thèse ont porté sur la conception et la réalisation d'un dispositif d'éclairage surfacique à géométrie planaire à base de structures plasmoniques, pour un fonctionnement à 633nm. Ce dispositif sera capable de convertir une lumière incidente cohérente en un faisceau de sortie uniforme sur la surface du dispositif, collimaté et avec un angle prédéfini par rapport au plan du dispositif. Pour réaliser ce dispositif, la solution envisagée est l'utilisation d'un réseau de guides d'onde diélectriques pour répartir la lumière sur la surface, et de chaînes de nano-structures d'argent couplées aux guides, dimensionnées comme des antennes pour réémettre la lumière hors du plan.Les travaux réalisés ont mis en évidence le contrôle du couplage entre le guide d'onde et la chaine de nano-structures d'argent, modulable par plusieurs paramètres dans une gamme comprise entre 10% et 90 % : nombre de particules, dimensions des particules, distance entre le guide et les particules. En jouant sur la période de la chaine, il est possible d'obtenir un rayonnement hors-plan, avec un angle déterminé par la formule des réseaux de diffraction. Des émetteurs élémentaires, composés d’un guide et de chaines de particules, ont été fabriquées en salle blanche et caractérisés sur un banc d’optique guidée à l'aide d'un montage de projection dans le plan de Fourier. Les diagrammes de rayonnement expérimentaux sont en accord avec les simulations. De premiers résultats ont également confirmé expérimentalement la possibilité de moduler le couplage guide-chaine en modifiant les dimensions des particules. Enfin le réseau de guides d'onde a été dimensionné pour une surface d'1 cm² et fabriqué en lithographie par projection. Les pertes linéiques mesurées dans les guides d'onde sont de l'ordre de 5 dB/mm. Plusieurs optimisations peuvent être réalisées pour améliorer la qualité des guides. A partir des données expérimentales obtenues et des simulations de propagation de faisceau, une configuration réaliste de dispositif d’éclairage incluant le nombre et le positionnement des émetteurs sur le réseau de guides a été proposée. L’ensemble des travaux réalisés valident l’approche choisie. / This work has focused on the design and realization of a planar lighting device based on plasmonic structures, for a 633nm operation. This device will be able to convert a coherent incident light into a uniform output beam over the surface of the device, collimated and with a predefined angle with respect to the plane of the device. To achieve this feature, the proposed solution is the use of an array of dielectric waveguides to distribute the light over the surface, and silver nanostructures chains coupled to the waveguides and dimensioned as antennas to retransmit the light out of the plane. The work carried out has highlighted the control of the coupling between the waveguide and the silver nanostructures chain, modulated by several parameters in a range between 10% and 90%: the number of particles, particle size, distance between the guide and the particles. By playing on the period of the chain, it is possible to obtain an out-of-plane radiation, with an angle determined by the diffraction gratings formula. Elementary emitters, consisting of a guide and particle chains, were manufactured in a clean room and characterized on a guided wave optical bench with Fourier plane projection set-up. The experimental radiation patterns are in agreement with the simulations one. First results have also experimentally confirmed the possibility of modulating the waveguide-chain coupling by modifying the dimensions of the particles. Finally, the waveguide network has been dimensioned for an 1 cm² surface and manufactured with projection lithography. The linear losses measured in the waveguides are of the order of 5 dB / mm. Several optimizations can be made to improve the quality of the guides. From the experimental data obtained and the beam propagation simulations, a realistic configuration of the lighting device including the number and positioning of the transmitters on the waveguide network has been proposed. All the works carried out validate the chosen approach.

Large scale data centers (DC) and high performance computing (HPC) systems require more and more computing power at higher energy efficiency. They are already consuming megawatts of power, and a linear extrapolation of trends reveals that they may eventually lead to unrealistic power consumption scenarios in order to satisfy future requirements (e.g., Exascale computing). Conventional complementary metal oxide semiconductor (CMOS)-based electronic interconnects are not expected to keep up with the envisioned future board-to-board and chip-to-chip (within multi-chip-modules) interconnect requirements because of bandwidth-density and power-consumption limitations. However, low-power and high-speed optics-based interconnects are emerging as alternatives for DC and HPC communications; they offer unique opportunities for continued energy-efficiency and bandwidth-density improvements, although cost is a challenge at the shortest length scales. Plasmonics-based interconnects on the other hand, due to their extremely small size, offer another interesting solution for further scaling operational speed and energy efficiency. At the device-level, CMOS compatibility is also an important issue, since ultimately photonics or plasmonics will have to be co-integrated with electronics. In this paper, we survey the available literature and compare the aforementioned interconnect technologies, with respect to their suitability for high-speed and energy-efficient on-chip and offchip communications. This paper refers to relatively short links with potential applications in the following interconnect distance hierarchy: local group of racks, board to board, module to module, chip to chip, and on chip connections. We compare different interconnect device modules, including low-energy output devices (such as lasers, modulators, and LEDs), photodetectors, passive devices (i.e., waveguides and couplers) and electrical circuitry (such as laserdiode drivers, modulator drivers, transimpedance, and limiting amplifiers). We show that photonic technologies have the potential to meet the requirements for selected HPC and DC applications in a shorter term. We also present that plasmonic interconnect modules could offer ultra-compact active areas, leading to high integration bandwidth densities, and low device capacitances allowing for ultra-high bandwidth operation that would satisfy the application requirements further into the future.

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Nowadays, as aging population increasing yearly, the health care technologies for elder people who commonly have high blood pressure or Glaucoma issues have attracted much attention. In order to care of those people, implantable integrated circuits (ICs) in human body are the direct solution to have 24/7 days monitoring with real-time data for diagnosis by patients themselves or doctors. However, due to the small size requirement for the implanted ICs located in human organs, it's quite challenging to integrate with transmitting and receiving antenna in a single chip, especially operating in 5.8-GHz ISM band. This research proposes a new idea to solve the issue of integrating an on-chip antenna with implanted ICs. By adding an additional dielectric substrate upon the layer of silicon oxide in CMOS technology, utilizing the metal-6, it can form an extremely compact 3D-structure on-chip antenna which is able to be placed in human eye, heart or even in a few mm-diameter vessels. The proposed 3D on-chip antenna is only 1x1x2.8 mm3 with -10 dB gain and 10% efficiency, which has capability to communicate at least within 5 cm distance. The entire implanted battery-less wireless system has also been developed in this research. A designed 30% efficiency Native NMOS rectifier could generate 1 V and 1 mA to supply the designed low power transmitter including voltage-controlled oscillator (VCO) and power amplifier (PA). The entire system performance is well evaluated by link budget analysis and the simulation result demonstrates the possibility and feasibility of future on-demand easy-to-design implantable SoC.

This work presents novel continuous-time delta-sigma modulator architectures with low-power consumption and improved signal transfer functions which are suitable for wideband A/D conversion in wireless applications, e.g., 3G and 4G receivers. The research has explored two routes for improving the overall performance of continuous-time delta-sigma modulator. The first part of this work proposes the use of the power efficient Successive-Approximations (SAR) architecture, instead of the conventional Flash ADC, as the internal quantizer of the delta-sigma modulator. The SAR intrinsic latency has been addressed by means of a faster clock for the quantizer as well as full-period delay compensation. The use of SAR quantizer allows for increasing the resolution while reducing the total power consumption and complexity. A higher resolution quantizer, made feasible by the SAR, would allow implementing more aggressive noise shaping to facilitate wideband delta-sigma A/D conversion at lower over-sampling-rates. As proof of concept, a first-order CT delta-sigma modulator with a 5-bit SAR quantizer is designed and implemented in a 130 nm CMOS process which achieves 62 dB dynamic range over 1.92 MHz signal bandwidth meeting the requirements of the WCDMA standard. The prototype modulator draws 3.1 mW from a single 1.2 V supply and occupies 0.36 mm2 of die area. The second part of this research addresses the issue of out-of-band peaking in the signal-transfer-function (STF) of the widely used feedforward structure. The STF peaking is harmful to the performance of the modulator as it allows an interferer to saturate the quantizer and result in severe harmonic distortion and instability. As a remedy to this problem a general low-pass and peaking-free STF design methodology has been proposed which allows for implementing an all-pole filter in the input signal path for any given NTF. Based on the proposed method, the STF peaking of any feedforward modulator can be eliminated using extra feed-in paths to all the integrator inputs. A major drawback of the conventional feedforward topology having low-pass STF is the large sensitivity of the STF to the coefficients. In particular, component mismatch, due to random errors in the relative values of individual resistors or capacitors, can significantly degrade the anti-aliasing of the CT modulator and give rise to the unwanted STF peaking. To solve this problem two new architectures, namely dual-feedback and dual-feed-in are proposed which allow us to synthesize a low-pass STF with a smaller number of coefficients than the feedforward structure. The dual-feedback structure which shows significantly lower sensitivity to coefficient mismatch is extensively analyzed and simulated. Also for proof of concept a third-order modulator is implemented in a 130 nm CMOS process which achieves 76 dB dynamic-range over 5 MHz signal bandwidth meeting, for example, the requirements of a DVB-H receiver standard. In addition the modulator shows 77 dB anti-aliasing and less than 0.1 dB worst-case STF peaking. The measured power consumption of the modulator is 6 mW from a single 1.2 V and the die area is 0.56 mm2.

As we move deep into nanometer regime of CMOS VLSI (45nm node and below), the device noise margin gets sharply eroded because of continuous lowering of device threshold voltage together with ever increasing rate of signal transitions driven by the consistent demand for higher performance. Sharp erosion of device noise margin vastly increases the likelihood of intermittent failures (also known as parametric failures) during device operation as opposed to permanent failures caused by physical defects introduced during manufacturing process. The major sources of intermittent failures are capacitive crosstalk between neighbor interconnects, abnormal drop in power supply voltage (also known as droop), localized thermal gradient, and soft errors caused by impact of high energy particles on semiconductor surface. In nanometer technology, these intermittent failures largely outnumber the permanent failures caused by physical defects. Therefore, it is of paramount importance to come up with efficient test generation and test application methods to accurately detect and characterize these classes of failures. Soft error rate (SER) is an important design metric used in semiconductor industry and represented by number of such errors encountered per Billion hours of device operation, known as Failure-In-Time (FIT) rate. Soft errors are rare events. Traditional techniques for SER characterization involve testing multiple devices in parallel, or testing the device while keeping it in a high energy neutron bombardment chamber to artificially accelerate the occurrence of single events. Motivated by the fact that measurement of SER incurs high time and cost overhead, in this thesis, we propose a two step approach: hii a new filtering technique based on amplitude of the noise pulse, which significantly reduces the set of soft error susceptible nodes to be considered for a given design; followed by hiii an Integer Linear Program (ILP)-based pattern generation technique that accelerates the SER characterization process by 1-2 orders of magnitude compared to the current state-of-the-art. During test application, it is important to distinguish between an intermittent failure and a permanent failure. Motivated by the fact that most of the intermittent failures are temporally sparse in nature, we present a novel design-for-testability (DFT) architecture which facilitates application of the same test vector twice in a row. The underlying assumption here is that a soft fail will not manifest its effect in two consecutive test cycles whereas the error caused by a physical defect will produce an identically corrupt output signature in both test cycles. Therefore, comparing the output signature for two consecutive applications of the same test vector will accurately distinguish between a soft fail and a hard fail. We show application of this DFT technique in measuring soft error rate as well as other circuit marginality related parametric failures, such as thermal hot-spot induced delay failures. A major contribution of this thesis lies on investigating the effect of multiple sources of noise acting together in exacerbating the noise effect even further. The existing literature on signal integrity verification and test falls short of taking the combined noise effects into account. We particularly focus on capacitive crosstalk on long signal nets. A typical long net is capacitively coupled with multiple aggressors and also tend to have multiple fanout gates. Gate leakage current that originates in fanout receivers, flows backward and terminates in the driver causing a shift in driver output voltage. This effect becomes more prominent as gate oxide is scaled more aggressively. In this thesis, we first present a dynamic simulation-based study to establish the significance of the problem, followed by proposing an automatic test pattern generation (ATPG) solution which uses 0-1 Integer Linear Program (ILP) to maximize the cumulative voltage noise at a given victim net due to crosstalk and gate leakage loading in conjunction with propagating the fault effect to an observation point. Pattern pairs generated by this technique are useful for both manufacturing test application as well as signal integrity verification for nanometer designs. This research opens up a new direction for studying nanometer noise effects and motivates us to extend the study to other noise sources in tandem including voltage drop and temperature effects.

The application of epitaxially grown, III-V semiconductor-based nanostructures to the development of electro-optical and all-optical switches is investigated through the fabrication and testing of integrated photonic devices designed using multimode interference (MMI) waveguides. The properties and limitations of the materials are explored with respect to the operation of those devices through electrical carrier injection and optical pumping. MMI waveguide geometry was employed as it offered advantages such as a very compact device footprint, low polarization sensitivity, large bandwidth and relaxed fabrication tolerances when compared with conventional single-mode waveguide formats. The first portion of this dissertation focuses on the characterization of the materials and material processing techniques for the monolithic integration of In0.15Ga0.85As/GaAs self-assembled quantum dots (SAQD) and InGaAsP/InGaAsP multiple quantum wells (MQW). Supplemental methods for post-growth bandgap tuning and waveguide formation were developed, including a plasma treatment process which is demonstrated to reliably inhibit thermally induced interdiffusion of Ga and In atoms in In0.15Ga0.85As/GaAs quantum dots. The process is comparable to the existing approach of capping the SAQD wafer with TiO2, while being simpler to implement along-side companion techniques such as impurity free vacancy disordering. Study of plasma-surface interactions in both wafer structures suggests that the effect may be dependent on the composition of the contact layer. The second portion of this work deals with the design, fabrication, and the testing of MMI switches which are used to investigate the limits of electrical current control when employing SAQD as the active core material. A variable power splitter based on a 3-dB MMI coupler is used to analyze the effects of sub-microsecond electrical current pulses in relation to carrier and thermal nonlinearities. Electrical current controlled switching of the variable power splitter and a tunable 2 x 2 MMI coupler is also demonstrated. The third part of this dissertation explores the response of In0.15Ga0.85As/GaAs SAQD waveguide structures to photogenerated carriers. Also presented is a simple, but effective, design modification to the 2 x 2 MMI cross-coupler switch that allows control over the carrier distribution within the MMI waveguide. This technique is combined with selective-area bandgap tuning to demonstrate a compact, working, all-optical MMI based switch.