The central thesis of this research is that VLSI interconnect design strategies should shift from using global wires that can support only a single binary transition during the latency of the line to global wires that can sustain multiple bits traveling simultaneously along the length of the line. It is shown in this thesis that such throughput-centric multibit transmission can be achieved by wave-pipelining the interconnects using repeaters. A holistic analysis of wave-pipelined interconnect circuits, along with the full-custom optimization of these circuits, is performed in this research. With the help of models and methodologies developed in this thesis, the design rules for repeater insertion are crafted to simultaneously optimize performance, power, and area of VLSI global interconnect networks through a simultaneous application of voltage scaling and wire sizing. A qualitative analysis of latency, throughput, signal integrity, power dissipation, and area is performed that compares the results of design optimizations in this work to those of conventional global interconnect circuits. The objective of this thesis is to study the circuit- and system-level opportunities of voltage scaling, wire sizing, and repeater insertion in wave-pipelined global interconnect networks that are implemented in deep submicron technologies.

This thesis presents an overview of the simulation, design, and measurement of state-of-the-art Silicon-Germanium Hetro-Junction Bipolar Transistor (SiGe HBT) low-noise amplifiers (LNAs). The LNA design trade-off space is presented and methods for achieving an optimized design are discussed. In Chapter 1, we review the importance of LNAs and the benefits of SiGe HBT technology in high frequency amplifier design. Chapter 2 introduces LNA design and basic noise theory. A graphical LNA design approach is presented to aid in understanding of the high-frequency LNA design process. Chapter 3 presents an LNA design optimization method for power constrained applications. Measured results using this design technique are highlighted and shown to have record performance. Lastly, in Chapter 4, we highlight cryogenic noise performance and present measured results from cryogenic operation of SiGe HBT LNAs. We demonstrate in this thesis that SiGe HBT LNAs have the capability to meet the demanding needs for next generation wireless systems. The aim of the analysis presented herein is to provide designers with the fundamentals of designing SiGe HBT LNAs through relevant design examples and measured results.

The primary objective of this research was to investigate and develop an electrostatic energy-harvesting voltage-constrained CMOS/BiCMOS integrated circuit (IC) that harnesses ambient kinetic energy from vibrations with a vibration-sensitive variable capacitor and channels the extracted energy to charge an energy-storage device (e.g., battery). The proposed harvester charges and holds the voltage across the vibration-sensitive variable capacitor so that vibrations can induce it to generate current into the battery when capacitance decreases (as its plates separate). To that end, the research developed an energy-harvesting system that synchronizes to variable capacitor's state as it cycles between maximum and minimum capacitance by controlling each functional phase of the harvester and adjusting to different voltages of the on-board battery. One of the major challenges of the system was performing all of these duties without dissipating the energy harnessed and gained from the environment. Consequently, the system reduces losses by time-managing and biasing its circuits to operate only when needed and with just enough energy while charging the capacitor through an efficient inductor-based precharger. As result, the proposed energy harvester stores a net energy gain in the battery during each vibration cycle.

Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection. This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.

For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.

As the current electronic trend is toward integrating multiple functions in a single electronic device, there is a clear need for increasing integration density which is becoming more emphasized than in the past. To meet the industrial need and realize the new system-integration law [1], three-dimensional (3-D) integration is becoming necessary. 3-D integration of multiple functional IC chip/package modules requires co-simulation of the chip and the package to evaluate the performance of the system accurately. Due to large scale differences in the physical dimensions of chip-package structures, the chip-package co-simulation in time-domain using the conventional FDTD scheme is challenging because of Courant-Friedrich-Levy (CFL) condition that limits the time step. Laguerre-FDTD has been proposed to overcome the limitations on the time step. To enhance performance and applicability, SLeEC methodology [2] has been proposed based on the Laguerre-FDTD method. However, the SLeEC method still has limitations to solve practical 3-D integration problems. This dissertation proposes further improvements of the Laguerre-FDTD and SLeEC method to address practical problems in 3-D interconnects and 3-D integration. A method that increases the accuracy in the conversion of the solutions from Laguerre-domain to time-domain is demonstrated. A methodology that enables the Laguerre-FDTD simulation for any length of time, which was challenging in prior work, is proposed. Therefore, the analysis of the low-frequency response can be performed from the time-domain simulation for a long time period. An efficient method to analyze frequency-domain response using time-domain simulations is introduced. Finally, to model practical structures, it is crucial to model dispersive materials. A Laguerre-FDTD formulation for frequency-dependent dispersive materials is derived in this dissertation and has been implemented.

The widespread use of Liquid Petroleum Gas (LPG) for cooking and as fuel for automobile vehicles requires fast and selective detection of LPG to precisely measure the leakage of gas for preventing the occurrence of accidental explosions. The adoption of Micro-Electro-Mechanical-System (MEMS) technology for fabricating the gas sensor provides other potential advantages for sensing applications, which includes low power consumption, low fabrication cost, high quality, small size and reliability. MEMS based gas sensor requires a sensitive layer of oxide material like ZnO, SnO2, TiO2, Fe2O3, etc. The tin oxide material used in the present work changes its electrical properties, as it interacts with the reducing gas like LPG. The sensor material becomes active only at high temperature such as 400ºC, thereby realizing the need of a micro heater to reach the desired temperature. To control the temperature of micro heater and to determine the change in electrical properties of the sensor due to its interaction with LPG an Application Specific Integrated Circuit (ASIC) forms an essential constituent of the MEMS based gas sensor. In the present work, an attempt has been made to improve the sensitivity of LPG gas sensor and it is correlated with other properties by different characterization techniques. The work also includes the design as well as testing of ASIC for gas sensor system. Process parameters particularly deposition time and substrate temperature have a profound influence on the microstructure of the tin oxide film, which in turn affects the gas sensing properties. To study the effects of these parameters, RF magnetron sputtering system is used for depositing tin oxide films onto the silicon substrate, which is compatible with CMOS technology. The effects of structural properties, optical properties and the porosity of the films are also studied and correlated with the gas sensing properties. In this direction the deposited films are characterized using X-Ray Diffraction (XRD) to determine the structure orientation. The morphology of the sensor films are analyzed by Scanning Electron Microscope (SEM) while the refractive index, thickness and porosity of the films are determined using ellipsometry studies. The thickness of the deposited films is also confirmed by the surface profilometer. The change in composition of the deposited film along its depth is determined using Secondary Ion Mass Spectrometer (SIMS). Maximum sensitivity 5.5 is obtained for 470 nm thick films, which corresponds to a grain size of 38nm at the operating temperature of 4000C. Following these studies, an ASIC has been designed using Tanner EDA Tools on AMIS 0.7 µm CMOS process, fabricated through Euro practice’s ASIC prototyping service, Belgium and tested successfully after fabrication. The temperature control module of ASIC has been designed using relaxation oscillator technique to control the temperature of the in house developed heater. The resistance to period conversion technique is explored for the design of the sensor read out module of ASIC. The heater is integrated successfully with the sensor film, ASIC and microcontroller based LCD module. The test results show good agreement with the simulation results.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009. / Includes bibliographical references.

Copper interconnect requires liner materials that function as a diffusion barrier, a seed layer for electroplating, and an adhesion promoting layer. Ruthenium has been considered as a promising liner material, however it has been reported that Ru itself is not an effective Cu diffusion barrier due to its microstructure, which is polycrystalline with columnar grains. The screening study of Ru precursors revealed that all Ru films were polycrystalline with columnar structure, and, due to its strong 3D growth mode, a conformal and ultrathin Ru film was difficult to form, especially on high aspect ratio features. The microstructure of Ru films can be modified by incorporating P. Amorphous Ru(P) films are formed by chemical vapor deposition at 575 K using a single source precursor, cis-RuH₂(P(CH₃)₃)₄, or dual sources, Ru₃(CO)₁₂ and P(CH₃)₃ or P(C6H5)₃ The films contain Ru and P, which are in zero-valent states, and C as an impurity. Phosphorus dominantly affects the film microstructure, and incorporating > 13% P resulted in amorphous Ru(P) films. Metastable Ru(P) remains amorphous after annealing at 675 K for 3 hr, and starts recrystallization at ~775 K. The density of states analysis of the amorphous Ru(P) alloy illustrates metallic character of the films, and hybridization between Ru 4d and P 3p orbitals, which contributes to stabilizing the amorphous structure. Co-dosing P(CH)₃ with Ru₃(CO)₁₂ improves film step coverage, and the most conformal Ru(P) film is obtained with cis-RuH2(P(CH₃)₃)₄; a fully continuous 5 nm Ru(P) film is formed within 1 µm deep, 8:1 aspect ratio trenches. First principles density functional theory calculations illustrate degraded Cu/Ru adhesion by the presence of P at the interface, however, due to the strong Ru-Cu bonds, amorphous Ru(P) forms a stronger interface with Cu than Ta and TaN do. Cu diffusion studies at 575 K suggests improved barrier property of amorphous Ru(P) films over polycrystalline PVD Ru.

M. Tech. Metallurgical Engineering. / Aims at improving Cu interconnection problem by homogeneous distribution of ruthenium and tantalum in Cu matrix for excellent interconnection in electronics packaging. The aim will be achieved through the following objectives.Development of appropriate technology for homogenizing submicron metal powders with suitable methods for controlling grain growth during sintering. Study the mechanisms of synergistic incorporation of Ru, and Ta on improving copper interconnection properties. To investigate metallurgical interactions and phenomena occurring during sintering. To investigate specific property and behaviour advantages intrinsic due to the composites and material mix.