This thesis is devoted to the research and development of low processing temperature lead-free interconnect materials for microelectronic packaging applications with an emphasis on fundamental studies of nanoparticles synthesis, dispersion and oxidation prevention, and nanocomposites fabrication. Oxide-free tin (Sn), tin/silver (96.5Sn3.5Ag) and tin/silver/copper (96.5Sn3.0Ag0.5Cu) alloy nanoparticles with different sizes were synthesized by a low temperature chemical reduction method. Both size dependent melting point and latent heat of fusion of the synthesized nanoparticles were obtained. The nano lead-free solder pastes/composites created by dispersing the SnAg or SnAgCu alloy nanoparticles into an acidic type flux spread and wet on the cleaned copper surface at 220 to 230 ¡æ. This study demonstrated the feasibility of nano sized SnAg or SnAgCu alloy particle pastes for low processing temperature lead-free interconnect applications in microelectronic packaging. Surface functionalized silver nanoparticles and silver fakes were used as fillers for electrically conductive adhesives (ECAs) applications. During the curing of epoxy resin (150 ¡æ), the surfactants were debonded from the particles and at the same time the oxide layers on the particle surfaces were removed which facilitated the sintering of Ag nanoparticles. The contact interfaces between fillers were significantly reduced and an ultra highly conductive ECA with a resistivity of 5 ¡Á 10-6 ohm.cm was obtained. To enhance the adhesion of carbon nanotube (CNT) films to substrates, an ultra highly conductive ECA were used as a media to transfer the CNT films to copper substrates. The polymer wetted along the CNTs during curing process by the capillary force. An ohmic contact was formed between the copper substrates and the transferred CNTs. This process could overcome the serious obstacles of integration of CNTs into integrated circuits and microelectronic device packages by offering low processing temperatures and improved adhesion of CNTs to substrates. The transferred CNTs can be used to simultaneously form electrical and mechanical connections between chips and substrates.

It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors (ITRS) that by the year 2019, with the IC feature size shrinking to about 10nm, off-chip interconnects in an area array format will require a pitch of 95 µm. Also, as the industry adopts porous low-K dielectric materials, it is important to ensure that the stresses induced by the off-chip interconnects and the package do not crack or delaminate the low-K material. Compliant free-standing structures used as off-chip interconnects are a potential solution. However, there are several design, fabrication, assembly and integration research challenges and gaps with the current suite of compliant interconnects. Accordingly, as part of this research a unique parallel-path approach has been developed which enhances the mechanical compliance of the compliant interconnect without compromising the electrical parasitics. It also provides for redundancy and thus results in more reliable interconnects. Also, to meet both electrical and mechanical performance needs, as part of this research a variable compliance approach has been developed so that interconnects near the center of the die have lower electrical parasitics while the interconnects near the corner of the die have higher mechanical compliance. Furthermore, this work has developed a fabrication process which will facilitate cost-effective fabrication of free-standing compliant interconnects and investigated key factors which impact assembly yield of free-standing compliant interconnects. Ultimately the proposed approaches are demonstrated by developing an innovative compliant interconnect called FlexConnects. Hence, through this research it is expected that the developed compliant interconnect would address the needs of first level interconnects over the next decade and eliminate a bottleneck that threatens to impede the exponential growth in microprocessor performance. Also, the concepts developed in this research are generic in nature and can be extended to other aspects of electronic packaging.

Electrically conductive adhesives (ECAs) are one of the lead-free interconnect materials with the advantages of environmental friendliness, mild processing conditions, fewer processing steps, low stress on the substrates, and fine pitch interconnect capability. However, some challenging issues still exist for the currently available ECAs, including lower electrical conductivity, conductivity fatigue in reliability tests, limited current-carrying capability, poor impact strength, etc. The interfacial properties is one of the major considerations when resolving these challenges and developing high performance conductive adhesives. Surface functionalization and interface modification are the major approaches used in this thesis. Fundamental understanding and analysis of the interaction between various types of interface modifiers and ECA materials and substrates are the key for the development of high performance ECA for lead-free interconnects. The results of this thesis provide the guideline for the enhancement of interfacial properties of metal-metal and metal-polymer interactions. Systematic investigation of various types of ECAs contributes to a better understanding of materials requirements for different applications, such as surface mount technology (SMT), flip chip applications, flat panel display modules with high resolution, etc. Improvement of the electrical, thermal and reliability of different ECAs make them a potentially ideal candidate for high power and fine pitch microelectronics packaging option.

As the convergence of multiple functions in a single electronic device drives current electronic trends, the need for increasing integration density is becoming more emphasized than in the past. To keep up with the industrial need and realize the new system integration law, three-dimensional (3-D) integration called System-on-Package (SoP) is becoming necessary. However, the commercialization of 3-D integration should overcome several technical barriers, one of which is the difficulty for the electrical design of interconnections. The 3-D interconnection design is difficult because of the modeling challenge of electrical coupling from the complicated structures of a large number of interconnections. In addition, mixed-signal design requires broadband modeling, which covers a large frequency spectrum for integrated microsystems. By using currently available methods, the electrical modeling of 3-D interconnections can be a very challenging task. This dissertation proposes a new method for constructing a broadband model of a large number of 3-D interconnections. The basic idea to address the many interconnections is using modal basis functions that capture electrical effects in interconnections. Since the use of global modal basis functions alleviates the need for discretization process of the interconnection structure, the computational cost is reduced considerably. The resultant interconnection model is a RLGC model that describes the broadband electrical behavior including losses and couplings. The smaller number of basis functions makes the interconnection model simpler, and therefore allows the generation of network parameters at reduced computational cost. Focusing on the modeling of bonding wires in stacked ICs and through-silicon via (TSV) interconnections, this research validates the interconnection modeling approach using several examples from 3-D full-wave EM simulation results.

Thesis (Ph. D.)--Ohio State University, 2007. / Full text release at OhioLINK's ETD Center delayed at author's request

Thesis (Ph. D.)--Ohio State University, 2005. / Title from first page of PDF file. Document formatted into pages; contains xvi, 136 p.; also includes graphics (some col.). Includes bibliographical references (p. 125-136). Available online via OhioLINK's ETD Center

Les recherches de cette thèse portent sur la mise en oeuvre des méthodes de la rechercheopérationnelle (RO) pour la conception de circuits numériques dans le domaine du traitementdu signal et de l’image, plus spécifiquement pour des applications multimédia et de visionembarquée.Face à la problématique de “Memory Wall”, les concepteurs de systèmes de vision embarquée,Mancini et al. (Proc.DATE, 2012), ont proposé un générateur de hiérarchies mémoiresad-hoc dénommé Memory Management Optimization (MMOpt). Cet atelier de conception estdestiné aux traitements non-linéaires afin d’optimiser la gestion des accès mémoires de cestraitements. Dans le cadre de l’outil MMOpt, nous abordons la problématique d’optimisationliée au fonctionnement efficace des circuits de traitement d’image générés par MMOpt visantl’amélioration des enjeux de performance (contrainte temps-réel), de consommation d’énergieet de coût de production (contrainte d’encombrement).Ce problème électronique a été modélisé comme un problème d’ordonnancement multiobjectif,appelé 3-objective Process Scheduling and Data Prefetching Problem (3-PSDPP), reflétantles 3 principaux enjeux électroniques considérés. À notre connaissance, ce problème n’apas été étudié avant dans la littérature de RO. Une revue de l’état de l’art sur les principaux travauxliés à cette thèse, y compris les travaux antérieurs proposés par Mancini et al. (Proc.DATE,2012) ainsi qu’un bref aperçu sur des problèmes voisins trouvés dans la littérature de RO,a ensuite été faite. En outre, la complexité de certaines variantes mono-objectif du problèmed’origine 3-PSDPP a été établie. Des approches de résolution, y compris les méthodes exactes(PLNE) et les heuristiques constructives, sont alors proposées. Enfin, la performance de cesméthodes a été comparée par rapport à l’algorithme actuellement utilisé dans l’outil MMOpt,sur des benchmarks disponibles dans la littérature ainsi que ceux fournis par Mancini et al.(Proc.DATE, 2012).Les solutions obtenues sont de très bonne qualité et présentent une piste prometteuse pouroptimiser les performances des hiérarchies mémoires produites par MMOpt. En revanche, vuque les besoins de l’utilisateur de l’outil sont contradictoires, il est impossible de parler d’unesolution unique en optimisant simultanément les trois critères considérés. Un ensemble debonnes solutions de compromis entre ces trois critères a été fourni. L’utilisateur de l’outilMMOpt peut alors décider de la solution qui lui est la mieux adaptée. / The research of this thesis focuses on the application of the Operations Research (OR)methodology to design new optimization algorithms to enable low cost and efficient embeddedvision systems, or more generally devices for multimedia applications such as signal and imageprocessing.The design of embedded vision systems faces the “Memory Wall” challenge regarding thehigh latency of memories holding big image data. For the case of non-linear image accesses, onesolution has been proposed by Mancini et al. (Proc. DATE 2012) in the form of a software tool,called Memory Management Optimization (MMOpt), that creates an ad-hoc memory hierarchiesfor such a treatment. It creates a circuit called a Tile Processing Unit (TPU) that containsthe circuit for the treatment. In this context, we address the optimization challenge set by theefficient operation of the circuits produced by MMOpt to enhance the 3 main electronic designcharacteristics. They correspond to the energy consumption, performance and size/productioncost of the circuit.This electronic problem is formalized as a 3-objective scheduling problem, which is called3-objective Process Scheduling and Data Prefetching Problem (3-PSDPP), reflecting the 3 mainelectronic design characteristics under consideration. To the best of our knowledge, this problemhas not been studied before in the OR literature. A review of the state of the art, including theprevious work proposed by Mancini et al. (Proc.DATE, 2012) as well as a brief overview onrelated problems found in the OR literature, is then made. In addition, the complexity of someof the mono-objective sub-problems of 3-PSDPP problem is established. Several resolutionapproaches, including exact methods (ILP) and polynomial constructive heuristics, are thenproposed. Finally, the performance of these methods is compared, on benchmarks available inthe literature, as well as those provided by Mancini et al. (Proc.DATE, 2012), against the onecurrently in use in the MMOpt tool.The results show that our algorithms perform well in terms of computational efficiency andsolution quality. They present a promising track to optimize the performance of the TPUs producedby MMOpt. However, since the user’s needs of the MMOpt tool are contradictory, such aslow cost, low energy and high performance, it is difficult to find a unique and optimal solutionto optimize simultaneously the three criteria under consideration. A set of good compromisesolutions between these three criteria was provided. The MMOpt’s user can then choose thebest compromise solution he wants or needs.

Um novo circuito amplificador de 50 MHz - 1 GHz com alta linearidade para o padrão IEEE 802.22 “wireless regional area” (WRAN) é apresentado. Ele foi implementado sem nenhum indutor e oferece uma saída diferencial para ser utilizada como balun. Técnicas de cancelamento de ruído e aumento de linearidade foram usadas para melhorar a performace do amplificador de modo que eles pudessem ser otimizados separadamente. A linearidade foi melhorada utilizando transistores conectados como diodo. O amplificador foi implementado em um processo CMOS 130 nm, em uma área compacta de 136 m x 71 m. As simulações são apresentadas para esquemáticos pós-leiaute para duas classes diferentes de projeto: um visando a melhor linearidade e o outro a melhor Figura de Ruído (FR). Quando otimizado para melhor linearidade, os resultados de simulação atingem um ganho de tensão > 23.7 dB (ganho de potência > 19.1 dB), uma figura de ruído < 3.6 dB na banda inteira (com 2.4 dB min), um ponto de intersecção de terceira ordem (IIP3) > 3.3 dBm (7.6 dBm max) e um coeficiente de reflexão de entrada S11 < -16 dB. Quando otimizado para melhor figura de ruído, ele atinge um ganho de tensão > 24.7 dB (ganho de potência > 19.8 dB), uma FR < 2 dB na banda inteira, um IIP3 > -0.3 dBm e um S11 < -11 dB. Resultados de simulação Monte Carlo confirmam baixa sensibilidade à variabilidade de processo. Além disso, uma baixa sensibilidade com a temperatura na faixa de -55 até 125 C foi observada para Ganho, FR e S11. Consumo de potência é 17.6 mA sob fonte de alimentação de 1.2 V. / A new 50 MHz - 1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network (WRAN) is presented. It was implemented without any inductor and offers a differential output for balun use. Noise cancelling and linearity boosting techniques were used to improve the amplifier performance in a way they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 m x 71 m area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain > 23.7 dB (power gain > 19.1 dB), a NF < 3.6 dB over the entire band (with 2.4 dB min figure), an input third-order intercept point (IIP3) > 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 < -16 dB. When optimized for best NF, it achieves a voltage gain > 24.7 dB (power gain > 19.8 dB), a NF < 2 dB over the entire band, an IIP3 > -0.3 dBm and an S11 < -11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range -55 to 125 C was observed for Gain, NF and S11. Power consumption is 17.6 mA under a 1.2 V supply.

Depuis plusieurs années de nombreuses technologies non volatiles sont apparues et ont pris place principalement dans le monde de la mémoire, tendant à remplacer tout type de mémoire. Leurs atouts laissent à penser que certaines d'entre elles, et en particulier les technologies MRAM, pourraient améliorer les performances des circuits intégrés en utilisant leurs composants magnétiques, si connus notamment sous le nom de jonctions tunnel magnétiques, dans la logique. Pour évaluer ces éventuels gains, il faut être capable de concevoir de tels circuits. C'est pourquoi nous proposons dans ces travaux d'une part un kit de conception complet pour les flots de conception full custom et numérique, permettant de couvrir l'ensemble des étapes de conception pour chacun d'entre eux. Une partie de ce kit a servi à plusieurs partenaires de projets de recherche ANR, pour concevoir des démonstrateurs. Nous proposons également dans ce kit de conception un latch magnétique non volatil innovant ultra compact, pour lequel deux brevets d'invention ont été déposés, intégré à une flip-flop. Enfin, nous présentons l'intégration de composants magnétiques à deux applications, sécurité et faible consommation, ainsi qu'une étude qui montre que les gains en consommation statique peuvent être considérables. / For several years many non-volatile technologies have been appearing and taking place mainly in the memory world, aiming at replacing all kind of memory. Their assets let thinking that some of them, specially the MRAM technologies, could improve the integrated circuit performances, using their so called magnetic components in the logic, in particular the magnetic tunnel junctions. To evaluate the potential benefits, it is necessary to be able to design such a circuit. That is the reason why we are proposing a full design kit for both full custom and digital designs, allowing all the design steps. Part of this kit has been used by partners in research project to design demonstrators. We also propose in this kit an innovative ultra-compact magnetic latch, for which 2 patents have been deposited, integrated in a flip-flop. Finally, we present the integration of magnetic components for two applications, security and low power, as well as a case study which shows that the static consumption reduction can be huge.

Submitted by Morgana Silva (morgana_linhares@yahoo.com.br) on 2016-08-08T19:40:34Z No. of bitstreams: 1 arquivototal.pdf: 3706352 bytes, checksum: 29aeb9abd002f9b433386245e34fc85b (MD5) / Made available in DSpace on 2016-08-08T19:40:34Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 3706352 bytes, checksum: 29aeb9abd002f9b433386245e34fc85b (MD5) Previous issue date: 2016-02-29 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / Conselho Nacional de Pesquisa e Desenvolvimento Científico e Tecnológico - CNPq / An integrated circuit (IC) in test mode has a higher energy consumption compared to the normal operating mode, due to the increased number of transitions in the nodes of the resulting circuit applying test patterns used to stimulate the CI during the test run resulting in high power dissipation which can damage the IC, resulting in higher costs for manufacturers. In this work we propose a genetic algorithm to optimize sequences of test patterns aiming at low energy consumption during the test run, maintaining an adequate fault coverage. It is also proposed using the Berlekamp-Massey algorithm to synthesize an integrated test patterns with low hardware sobreárea generator capable of generating sequences optimized based on Shift Register with Linear Feedback. The optimization of the sequences is done by reducing the number of transitions at nodes whose evaluation is done by a computer program developed in this study in C ++. Finally, simulations were performed with the genetic algorithm to check the behavior to optimize the number of transitions, the fault coverage and hardware sobreárea. / Um circuito integrado (CI) em modo de teste apresenta um maior consumo energético comparado ao modo de operação normal, devido ao aumento do número de transições nos nós do circuito decorrentes da aplicação de padrões de teste utilizados para estimular o CI durante a execução do teste resultando em uma alta dissipação de potência que pode danificar o CI, acarretando em maiores custos para as fabricantes. Assim, neste trabalho é proposto um algoritmo genético para otimização de sequências de padrões de teste visando o baixo consumo energético, durante a execução do teste, mantendo uma adequada cobertura de falhas. É proposto também o uso do algoritmo de Berlekamp-Massey para sintetizar um gerador integrado de padrões de teste com baixa sobreárea de hardware capaz de gerar as sequências otimizadas baseado em Registrador de Deslocamento com Realimentação Linear. A otimização das sequências é feita através da redução do número de transições nos nós cuja avaliação é feita por um programa de computador desenvolvido nesta pesquisa em C++. Por fim, simulações foram realizadas com o algoritmo genético para verificar o comportamento em relação a otimização do número de transições, da cobertura de falhas e da sobreárea de hardware.