This thesis deals with non-conventional applications in the area of thick film technology, especially with indication of the temperature by thermodynamic sensors. The work summarizes thermodynamic sensors theory and also contains production data of the universal thermodynamic sensor realized on ceramic substrate, including measurement of its parameters and heat radiation.

Die vorliegende Arbeit behandelt den Entwurf eines ADCs nach dem sukzessiven Approximationsverfahren (SAR). Ausgehend von den Systemanforderungen erfolgt eine Ableitung der Spezifikation des zu entwerfenden ADCs. Theoretische Betrachtungen und Highlevelsimulationen in Matlab wählen die optimale Architektur der Einzelkomponenten - kapazitives DAC Array, Komparator, Ablaufsteuerung - aus. Die Implementation selbst findet für die Analogschaltungsteile auf Transistorebene und für die digitalen Komponenten auf RT-Ebene in VHDL statt. Sie bilden die Grundlage für die Realisierung des Layouts. In dem Zusammenhang stellt die Arbeit die gängigsten Matchingmethoden für elektronische Bauelemente vor. Abschließende PEX-Simulationen (parasitic Extraction) ermitteln die statischen (INL/DNL) wie dynamischen Kennwerte (SNR) des SAR-ADCs.:Abkürzungsverzeichnis iii Formelzeichen v 1 Einleitung 1 2 Grundlagen 2 2.1 Analog/Digital-Umsetzer 2 2.1.1 Umsetzungsverfahren 2 2.1.2 Statische Kennwerte 8 2.1.3 Dynamische Kennwerte 12 2.2 Technologie 17 2.2.1 Übersicht 17 2.2.2 MOS-Transistoren 17 2.2.3 Kapazitäten 18 2.2.4 Widerstände 18 2.3 Hardwarebeschreibungssprache 19 2.3.1 Übersicht 19 2.3.2 Zustandsautomat 19 2.3.3 Look-Ahead-Ausgang 20 3 Spezifikation 21 4 ADU-Topologie 23 4.1 Vorüberlegungen 23 4.1.1 Umsetzungsverfahren 23 4.1.2 Vergleich Widerstand/Kapazität 23 4.1.3 Differenziell Vs. Single-Ended 24 4.1.4 Kapazitätsarray 25 4.2 ADC High-Level Modell 30 4.2.1 Funktionsblöcke 30 4.2.2 Matlab/Simulink 31 4.2.3 Simulation 34 4.3 Parasitäre Effekte 37 4.3.1 Substratkapazität 37 4.3.2 Komparatoroffset 39 5 Schaltungsdesign & -simulation 41 5.1 Komparator 41 5.1.1 Spezifikation 41 5.1.2 Latch 41 5.1.3 Vorverstärker 43 5.1.4 Gesamtsystem 46 5.2 Schalter 46 5.2.1 Funktionsweise 46 5.2.2 Ladungseintrag 46 5.2.3 Dimensionierung & Simulation 47 5.3 Kapazitätsarray 51 5.4 SAR-Controller 51 5.4.1 Vorüberlegung 51 5.4.2 RTL Design 52 5.4.3 Simulation 55 5.4.4 Synthese 57 5.4.5 Optimierung 59 5.5 ADC (Toplevel) 59 5.5.1 Architektur 59 5.5.2 Simulation 61 6 Layout 64 6.1 Komparator 65 6.1.1 Vorverstärker 1 65 6.1.2 Vorverstärker 2 66 6.1.3 Dynamisches Latch 66 6.2 Transmission Gates 67 6.3 Kapazitätsarray 68 6.4 SAR-Controller 70 6.5 ADC (Toplevel) 70 6.6 PEX Simulation 72 6.6.1 Statischer Test 72 6.6.2 Dynamischer Test 73 7 Zusammenfassung 74 Literaturverzeichnis 76 Bücher 76 Skripte und Schriften 76 Internetlinks 78 Abbildungsverzeichnis 79 Tabellenverzeichnis 82 Anhang 84

Spin torque oscillator (STO) technology has a unique blend of features, including but not limited to octave tunability, GHz operating frequency, and nanoscaled size, which makes it highly suitable for microwave and radar applications. This thesis studies the fundamentals of STOs, utilizes the state-of-art STO's advantages, and proposes two STO-based microwave systems targeting its microwave applications and measurement setup, respectively. First, based on an investigation of possible STO applications, the magnetic tunnel junction (MTJ) STO shows a great suitability for microwave oscillator in multi-standard multi-band radios. Yet, it also imposes a large challenge due to its low output power, which limits it from being used as a microwave oscillator. In this regard, different power enhancement approaches are investigated to achieve an MTJ STO-based microwave oscillator. The only possible approach is to use a dedicated CMOS wideband amplifier to boost the output power of the MTJ STO. The dedicated wideband amplifier, containing a novel Balun-LNA, an amplification stage and an output buffer, is proposed, analyzed, implemented, measured and used to achieve the MTJ STO-based microwave oscillator. The proposed amplifier core consumes 25.44 mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nm CMOS process. The measurement results show a S21 of 35 dB, maximum NF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as the measurement results of the proposed MTJ STO-based microwave oscillator, show that this microwave oscillator has a highly-tunable range and is able to drive a PLL. The second aspect of this thesis, firstly identifies the major difficulties in measuring the giant magnetoresistance (GMR) STO, and hence studying its dynamic properties. Thereafter, the system architecture of a reliable GMR STO measurement setup, which integrates the GMR STO with a dedicated CMOS high frequency IC to overcome these difficulties in precise characterization of GMR STOs, is proposed. An analysis of integration methods is given and the integration method based on wire bonding is evaluated and employed, as a first integration attempt of STO and CMOS technologies. Moreover, a dedicated high frequency CMOS IC, which is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage for amplifying the weak signal generated by the GMR STO, is proposed, analyzed, developed, implemented and measured. The proposed dedicated high frequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power supply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. The proposed on-chip bias-tee presents a maximum measured S12 of -20 dB and a current handling of about 25 mA. Additionally, the proposed dedicated IC gives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz. The first attempt to measure the (GMR STO+IC) pair presents no RF signal at the output. The possible cause and other identified issues are given. / <p>QC 20140114</p>

<p>QC 20140609</p>

This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm². The driver can achieve an error-free (<BER < 10^12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 2^7-1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

No description available.

<p>Glaucoma is the leading cause of irreversible blindness worldwide. While current therapies aim to lower elevated intraocular pressure (IOP) to prevent blindness, they often do not provide the desired long-term efficacy, can fail over time, and have systemic side effects. Electroceutical stimulation can be a solution to many of these current issues with glaucoma treatment, as it is believed to have fewer systemic side effects and quicker response times. The goal of this work is to develop and demonstrate a novel system using electrical stimulation to lower intraocular pressure. I present data from a human clinical study and an ongoing clinical trial of the IOPTx™ system, a wearable electroceutical for treating glaucoma, that provides preliminary evidence of efficacy and safety. <a>Furthermore, no current glaucoma treatments allow for closed-loop, continuous monitoring of IOP, requiring more frequent doctor visits or forcing patients and clinicians to operate in the dark. Using an electroceutical therapeutic device with closed-loop feedback and continuous IOP recording can improve glaucoma management. I combined a pressure sensor with this electroceutical therapy, implanted the sensor and stimulation coils in rabbits, and stimulated the eyes. However, to better understand the optimal stimulation parameters, long-term effects, and mechanisms of action, an integrated circuit is designed as part of a fully implantable, closed-loop device. The chip was fabricated in 0.18 </a>µm CMOS process and validated on the benchtop and <i>in vivo</i>. In the future, this electroceutical device has the potential to be a novel treatment for patients suffering from glaucoma.</p>

Die vorliegende Arbeit befasst sich mit dem Entwurf eines monolithisch integrierten 60-GHz-Empfängerschaltkreises in einer modernen Silizium-Germanium-Halbleitertechnologie mit 190 GHz maximaler Transitfrequenz. Drei für die Entwicklung von MMIC-Empfängerschaltkreisen äußerst wichtige Prinzipien liegen dem Entwurf zugrunde: die Optimierung von Rauschverhalten und Bandbreite sowie die Betrachtung der maximal erreichbaren Ausgangsleistung. Diese Prinzipien werden detailliert untersucht und typische Schaltungen dahingehend analysiert. Insbesondere wird eine Methode vorgestellt, die es erlaubt, die maximale Ausgangsleistung für die häufig verwendete Kaskodestufe vorherzusagen. Dabei handelt es sich um eine Erweiterung der Methode der Lastkurve nach Cripps. Weiterhin werden Ansätze zur Modellierung von Leitungen vorgestellt und ihre Verwendbarkeit für die unterschiedlichen Simulationsarten diskutiert. Der Hauptteil der Arbeit behandelt den Entwurf des Empfängerschaltkreises, welcher aus einem breitbandigen Eingangsverstärker mit niedrigem Rauschen und einstellbarer Verstärkung, einem Leistungsteiler, einem direkten Quadratur-Abwärtsmischer, einem Basisbandverstärker, einem Treiberverstärker für das Lokaloszillatorsignal sowie einem 90°-Phasenschieber besteht. Zusätzlich sind verschiedene Referenzstrom- und -spannungsquellen im Schaltkreis integriert. Die gefertigte Schaltung wurde messtechnisch vollständig charakterisiert, und alle Ergebnisse sind wiedergegeben. Der gemessene Mischgewinn beträgt bis zu 40 dB bei einer Bandbreite von mehr als 15 GHz. Die Zweiseitenbandrauschzahl liegt bei moderaten 7,5 dB. Die gemessene Phasen- und Amplitudenabweichung sind geringer als 5° und geringer als 0,15 dB. Die Gesamtschaltung nimmt 360 mW Leistung aus einer 2,2-V-Spannungsquelle auf. Insbesondere die Bandbreite des Empfängerschaltkreises stellt eine Verbesserung des aktuellen Standes der Technik dar. / The present work studies the development of a monolithic 60 GHz receiver IC in a modern 190 GHz-fT silicon-germanium semiconductor technology. The design is based on three fundamental principles, which are of great importance for MMIC receiver design: noise optimisation, bandwidth enhancement and output power considerations. Those principles are discussed in detail, and typical circuit examples are comprehensively analysed. Specifically, a method is presented that allows the prediction of output power for the frequently-used cascode stage. This method is an extension of Cripps’ load line theory. Furthermore, modelling approaches for transmission lines and their suitability for various types of simulations are discussed. The main part focuses on the design process of the receiver IC, which consists of a broadband low noise amplifier with variable gain, a power divider, a zero-IF quadrature mixer, a baseband amplifier, an LO driver amplifier and a 90°-phase shifter. Additionally, several reference current and voltage sources are implemented in the IC. The manufactured circuit is characterised in detail, and all measurement results are presented. Over a bandwidth of more than 15 GHz, the measured conversion gain is up to 40 dB with a moderate double sideband noise figure of 7.5 dB. An I/Q imbalance measurement reveals a phase accuracy of better than 5° and an amplitude error of less than 0.15 dB. The total power consumption is 360 mW from a 2.2 V-source. Particularly in terms of bandwidth, the circuit performance exceeds the current state of the art.

No description available.

This thesis addresses basic scientific research in the field of transmitter front-end circuits for electro-optical data communication. First, the theoretical fundamentals are presented and analyzed. Based on the theoretical considerations, conceptual circuit designs are studied. Finally, in order to prove the described concepts, the circuits were experimentally characterized and subsequently compared to other works in the literature. The analysis covers key theoretical aspects regarding transmitter front-end circuits. It starts from the basic physical effects inside a transistor and ends with the design of high-swing modulator drivers. Furthermore, it comprises the fundamentals of optical modulators as well as the integration of the electrical driver with the modulator. First, the concept of a basic monolithically integrated transmitter consisting of a Mach-Zehnder modulator (MZM) and an electrical driver is presented. The circuit reaches a bit-error-free data rate of 37 Gb/s, which is a record among other monolithically integrated transmitters reported in the literature. It was shown that by employing a high-swing driver, high extinction ratios (ER) can be achieved (namely 8.4 dB at 25 Gb/s and 7.6 dB at 35 Gb/s) while using short-length phase shifters (2 mm of length). It was therefore proved that one of the main drawbacks of the MZM-based transmitters, namely their large chip area, can be mitigated by using high-swing drivers, however without sacrificing the ER. Next, an improved modulator driver design is investigated, the focus of the study being the linearity. In addition to a high peak-to-peak differential output voltage swing of 7.2 Vpp,d, the driver achieves record-low total harmonic distortion (THD) values of 1% (at 1 GHz, for the output swing of 6.5 Vpp,d) and 1.7% (at 1 GHz, for the output swing of 7 Vpp,d). Moreover, the driver reaches a bandwidth of 61.2 GHz and shows a high power efficiency when relating its DC power consumption to its output voltage swing. The achievement of a high linearity and bandwidth without an increased power consumption is due to the fact that the bias currents of the emitter-follower (EF) stages are provided by means of resistors instead of the conventional current sources. The two approaches were first analyzed mathematically and subsequently compared by means of circuit simulations. It was shown that the proposed approach for the realization of the EFs – i.e. by means of resistors – allows a reduction of the DC power consumption by 19% compared to the current-source approach for an equivalent performance in terms of linearity and bandwidth. Finally, a modulator driver concept suitable for higher-order modulation formats is studied, namely the 8-level pulse amplitude modulation (PAM-8). The circuit was realized as a 3-bit digital-to-analog converter (DAC), thus being able to yield 8-level output signals. Moreover, the circuit is able to function as a PAM-4 driver as well, thanks to the tunable tail currents of the DAC core. It achieves a symbol rate of 50 Gbaud, which corresponds to a bit rate of 150 Gb/s for the PAM-8 modulation and 100 Gb/s for PAM-4. The study showed that a modulator driver can be realized that is able to switch between different modulation formats (namely PAM-8 and PAM-4), without requiring extra power or additional circuit parts. Moreover, the use of on-chip single-to-differential converters (SDCs) targets the relaxation of the requirements on the stages that precede the driver. Finally, relating its DC power consumption (590 mW, including the SDCs) to its output voltage swing (4 Vpp,d), the driver shows one of the highest power efficiencies among PAM modulator drivers in the literature.