The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

The miniaturization of dc–dc switch-mode power supplies (SMPS) is of a key importance in volume-sensitive portable devices, such as cell phones, tablet computers, and digital cameras. In these systems, multiple SMPS are required to provide well regulated voltage and power to various electronic components such as the central processing unit (CPU) and random-access memory (RAM). The combined volume, weight, and surface area footprint of these SMPS is usually the largest component. Traditionally, SMPS volume reduction has been achieved through increased switching frequencies; however, for power-sensitive applications this is undesirable due to the increased switching losses. This thesis presents two alternative, power-efficient, SMPS miniaturization methods: one control and one topology based. The presented controller recovers from load transients with virtually minimum possible output voltage deviation, reducing the reactive component size. The controller utilizes a simple algorithm, requiring no knowledge of the converter parameters and virtually no processing power. The simplicity of the control concept enabled the design of an area and power efficient integrated circuit (IC) implementation. The entire IC is implemented in a CMOS 0.18µm process on a 0.26 mm2 silicon area, which is comparable to the state-of-the-art analog solutions. For the experimental system the deviation (output capacitor size) is about four times smaller than that of a fast PID compensator having a 1/10th of the switching frequency bandwidth. The second solution is a complementary converter topology that has a smaller output filter volume, improved dynamic response, and lower switching losses compared to the state-of-the-art solutions. To reduce the volume and switching losses, the input-to-output voltage difference is decreased with a capacitive attenuator that replaces the input filter capacitor and has approximately the same volume. Both the attenuator and the downstream buck converter share the same set of switches, minimizing conduction losses. A single multi-mode digital controller governs operation of both stages, seamlessly regulating the output and input center-tap voltages. Experiments with a 5–1.5-V, 2.5-A, 1-MHz prototype show that, compared to the conventional buck, the merged topology has 43% smaller inductor, 36% smaller output capacitor, up to 30% lower power losses, and a 25% faster transient response.

The PhD thesis focuses on the always-on low power SRAM memories (essentially low dynamic power) in thin CMOS technology node CMOS 32nm and beyond. It reviews the state of the art of the eSRAM and describes different techniques to reduce the static and dynamic power consumption with respect the variability issue. Main techniques of power reduction are reviewed with their contributions and their limitations. It presents also a discussion about a statistical variability modeling and the variability effects on the yield. An original low power architecture based on 5T-Portless bit-cell is presented, with current mode read/write operations, as an ideal candidate for the always-on SRAM memories. A test chip implementation in CMOS 32nm of the 5T-Porless is designed and a comparison with an existing 6T SRAM memory is presented based on simulation. Some test chip functionality results and power consumption are performed. Finally the conclusion highlights the major contributions of the study and discusses the various simplification assumptions to see possible limitations. It is concluded affirmatively about industrial interest of the 5T-Portless SRAM for always-on embedded applications. Perspectives concern the analytical modeling for statistical behavior of SRAM as the Monte-Carlo approach is no more practicable. The migration of the 5T-Portless SRAM may be already considered in advanced nodes.

No description available.

Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d'entretien de type Colpitts,la mise en forme et jusqu'à l'adaptation du signal à sa charge d'utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s'orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del'architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l'avons reportée par flip chip sur une interfacespécifique pour

The international technology roadmap for semiconductors (ITRS) 2012 report foresees the use of porous dielectric materials with a low dielectric constant in conjunction with copper interconnects as a way to reduce the resistive-capacitive (RC) delay in microelectronic applications. However, the introduction of pores in the dielectric not only serves as stress raisers but also diminishes the structural strength of the material. The challenge therefore with the implementation of low-k dielectrics for high-performance flip-chip packages is to create a reliable die to organic substrate interconnect solution which induces low stresses on the die to prevent the cohesive cracking and the interfacial delamination of the dielectric material. Potential interconnect solutions that meet this challenge are MEMS-like compliant freestanding micro-structures. These structures are designed to work as spring-like elements which allow the free lateral and out-of-plane motion between the silicon die and the organic substrate under assembly conditions as well as under thermal or power cycling. Thus, the focus of this research is to design, fabricate, and characterize electrically and mechanically an innovative compliant interconnect approach that addresses these challenges. The proposed interconnect is scalable in dimensions and pitch, and consists multiple electrical paths which will provide redundancy against interconnect failure. The multi-path design employs parallel electrical paths which effectively split a larger cross-sectional area into several smaller areas making the overall design more compliant than otherwise. This research proposes wafer-level, high-yield, CMOS-compatible fabrication procedure using sequential photolithography and copper electroplating. The proposed interconnects are symmetric and are amenable to easy reflow assembly to substrates. The mechanical compliance of the fabricated structures is studied through nano-indentation, while the electrical characteristics are assessed through fabricated prototypes. The xvi thermo-mechanical reliability of compliant interconnects is also demonstrated. Lastly, the dimensional scalability of the interconnects is also demonstrated.

Multi-chip integration with emerging technologies such as a 3D IC stack or 2.5D interposer is primarily enabled by the off-chip interconnections. The I/O density, speed and bandwidth requirements for emerging mobile and high-performance systems are projected to drive the interconnection pitch to less than 20 microns by 2015. A new class of low-temperature, low-pressure, high-throughput, cost-effective and maufacturable technologies are needed to enable such fine-pitch interconnections. A range of interconnection technologies are being pursued to achieve these fine-pitch interconnections, most notably direct Cu-Cu interconnections and copper pillars with solder caps. Direct Cu-Cu bonding has been a target in the semiconductor industry due to the high electrical and thermal conductivity of copper, its high current-carrying capability and compatibility with CMOS BEOL processes. However, stringent coplanarity requirements and high temperature and high pressure bonding needed for assembly have been the major barriers for this technology. Copper-solder interconnection technology has therefore become the main workhouse for off-chip interconnections, and has recently been demonstrated at pitches as low as 40 microns. However, the current interconnection approaches using copper-solder structures are not scalable to finer feature sizes due to electromigration, and reliability issues arising with decreased solder content. Solid Liquid Inter-Diffusion (SLID) bonding is a promising solution to achieve ultra-fine-pitch and ultra-short interconnections with a copper-solder system, as it relies on the conversion of the entire solder volume into thermally-stable and highly electromigration-resistant intermetallics with no residual solder. Such a complete conversion of solders to stable intermetallics, however, relies on a long assembly time or a subsequent post-annealing process. To achieve pitches lower than 30 micron pitch, this research aims to study two ultra-short copper-solder interconnection approaches: (i) copper pillar and solder cap technology, and (ii) a novel technology which will enable interconnections with improved electrical performance by fast and complete conversion of solders to stable intermetallics (IMCs) using Solid Liquid Diffusion (SLID) bonding approach. SLID bonding, being a liquid state diffusion process, combined with a novel, alternate layered copper-solder bump structure, leads to higher diffusion rates and a much faster conversion of solder to IMCs. Moreover this assembly bonding is done at a much lower temperature and pressure as compared to that used for Cu-Cu interconnections. FEM was used to study the effect of various assembly and bump-design characteristics on the post-assembly stress distribution in the ultra-short copper-solder joints, and design guidelines were evolved based on these results. Test vehicles, based on these guidelines, were designed and fabricated at 50 and 100 micron pitch for experimental analysis. The bumping process was optimized, and the effect of current density on the solder composition, bump-height non-uniformity and surface morphology of the deposited solder were studied. Ultra-short interconnections formed using the copper pillar and solder cap technology were characterized. A novel multi-layered copper-solder stack was designed based on diffusion modeling to optimize the bump stack configuration for high-throughput conversion to stable Cu3Sn intermetallic. Following this modeling, a novel bumping process with alternating copper and tin plating layers to predesigned thicknesses was then developed to fabricate the interconnection structure. Alternate layers of copper and tin were electroplated on a blanket wafer, as a first demonstration of this stack-technology. Dies with copper-solder test structures were bonded using SLID bonding to validate the formation of stable intermetallics.

This thesis examines second-order optical nonlinear wave mixing processes in domain-disordered quasi-phase matching waveguides and evaluates their potential use in compact, monolithically integrated wavelength conversion devices. The devices are based on a GaAs/AlGaAs superlattice-core waveguide structure with an improved design over previous generations. Quantum-well intermixing by ion-implantation is used to create the quasi-phase matching gratings in which the nonlinear susceptibility is periodically suppressed. Photoluminescence experiments showed a large band gap energy blue shift around 70 nm after intermixing. Measured two-photon absorption coefficients showed a significant polarization dependence and suppression of up to 80% after intermixing. Similar polarization dependencies and suppression were observed in three-photon absorption and nonlinear refraction. Advanced modeling of second-harmonic generation showed reductions of over 50% in efficiency due to linear losses alone. Self-phase modulation was found to be the dominant parasitic nonlinear effect on the conversion efficiency, with reductions of over 60%. Simulations of group velocity mismatch showed modest reductions in efficiency of less than 10%. Experiments on second-harmonic generation showed improvements in efficiency over previous generations due to low linear loss and improved intermixing. The improvements permitted demonstration of continuous wave second-harmonic generation for the first time in such structures with output power exceeding 1 µW. Also, Type-II phase matching was demonstrated for the first time. Saturation was observed as the power was increased, which, as predicted, was the result of self-phase modulation when using 2 ps pulses. By using 20 ps pulses instead, saturation effects were avoided. Thermo-optically induced bistability was observed in continuous wave experiments. Difference frequency generation was demonstrated with wavelengths from the optical C-band being converted to the L- and U-bands with continuous waves. Conversion for Type-I phase matching was demonstrated over 20 nm with signal and idler wavelengths being separated by over 100 nm. Type-II phase matched conversion was also observed. Using the experimental data for analysis, self-pumped conversion devices were found to require external amplification to reach practical output powers. Threshold pump powers for optical parametric oscillators were calculated to be impractically large. Proposed improvements to the device design are predicted to allow more practical operation of integrated conversion devices based on quasi-phase matching superlattice waveguides.

The dissertation investigates the optical time domain reflectometer (OTDR) systems. The main object of research is an optical receiver for OTDR. The aim of the work is to create an optical receiver design method-ology to achieve optimal dynamic range of the system for a given band-width, design and investigate integrated fully differential variable gain tran-simpedance amplifier for OTDR optical receiver. Main tasks solved in this work are: perform analysis of OTDR struc-tures, main specifications and suggest possible improvement approaches; analyze main optical receiver noise sources and noise minimization and create generalized noise model; create optical receiver for an OTDR design methodology, that allow calculating avalanche photodiode multiplication factor, transimpedance amplifier feedback resistance and voltage amplifier input transistor dimensions that achieves optimal OTDR dynamic range; design and perform simulations of transimpedance amplifier integrated cir-cuit using AMS 0.35 µm CMOS technology and calculate optical receiver parameters in 0.1–100 MHz range of bandwidths The dissertation consists of four parts including Introduction, 4 chap-ters, Conclusions, References and 1 Annex. The introduction reveals the investigated problem, importance of the thesis and the object of research. It also describes the purpose and tasks, research methodology, scientific novelty, the practical significance of re-sults examined in the paper and defended statements. The... [to full text] / Disertacijoje nagrinėjamos laiko srities optinės reflektometrinės (OTDR) sistemos. Pagrindinis tyrimo objektas yra OTDR įėjimo pakopa – optinis imtuvas (OI). Disertacijos tikslas – sukurti OI projektavimo metodiką, lei-džiančią pasiekti optimalų dinaminį diapazoną, suprojektuoti ir ištirti integ-rinį diferencinį pereinamos varžos stiprintuvą (PVS) su kintamu stiprinimo koeficientu. Darbe sprendžiami šie uždaviniai: atliekama OTDR ir jų pagrindinių charakteristikų analizė ir formuluojamos tobulinimo kryptys; analizuojami pagrindiniai optinio imtuvo triukšmų šaltiniai, jų mažinimo galimybės ir su-daromas apibendrintas optinio imtuvo triukšmų modelis; sukuriama OI pro-jektavimo metodika, leidžianti apskaičiuoti griūtinio fotodiodo dauginimo faktorių, pereinamosios varžos stiprintuvo grįžtamojo ryšio varžą ir įėjimo tranzistoriaus fizinius matmenis, kuriems esant gaunamas optimalus dina-minis diapazonas; projektuojamas optinio imtuvo maketas iš diskrečiųjų elementų ir tiriami jo parametrai; atliekamas integrinio PVS projektavimas ir modeliavimas, taikant 0,35 µm KMOP technologiją bei optinio imtuvo pa-rametrų skaičiavimas 0,1–100 MHz dažnių juostų diapazone. Disertaciją sudaro įvadas ir keturi skyriai. Pabaigoje pateikiami naudo-tos literatūros ir autoriaus publikacijų disertacijos tema sąrašai ir 1 priedas. Įvadiniame skyriuje aptariama: tiriamoji problema, darbo aktualumas, aprašomas tyrimų objektas, suformuluotas darbo tikslas bei uždaviniai, ap-rašoma tyrimų metodika... [toliau žr. visą tekstą]

Materials, Processes, and Characterization of Extended Air-gaps for the Intra-level Interconnection of Integrated Circuits Seongho Park 157 pages Directed by Dr. Paul A. Kohl and Dr. Sue Ann Bidstrup Allen The integration of an air-gap as an ultra low dielectric constant material in an intra-metal dielectric region of interconnect structure in integrated circuits was investigated in terms of material properties of a thermally decomposable sacrificial polymer, fabrication processes and electrical performance. Extension of the air-gap into the inter-layer dielectric region reduces the interconnect capacitance. In order to enhance the hardness of a polymer for the better process reliabilities, a conventional norbornene-based sacrificial polymer was electron-beam irradiated. Although the hardness of the polymer increased, the thermal properties degraded. A new high modulus tetracyclododecene-based sacrificial polymer was characterized and compared to the norbornene-based polymer in terms of hardness, process reliability and thermal properties. The tetracyclododecene-based polymer was harder and showed better process reliability than the norbornene-based sacrificial polymer. Using the tetracyclododecene-based sacrificial polymer, a single layer Cu/air-gap and extended Cu/air-gap structures were fabricated. The effective dielectric constant of the air-gap and extended air-gap structures were 2.42 and 2.17, respectively. This meets the requirements for the 32 nm node. Moisture uptake of the extended Cu/air-gap structure increased the effective dielectric constant. The exposure of the structure to hexamethyldisilazane vapor removed the absorbed moisture and changed the structure hydrophobic, improving the integration reliability. The integration processes of the air-gap and the extended air-gap into a dual damascene Cu metallization process has been proposed compared to state-of-the-art integration approaches.