A novel hierarchical flexing and stretching strategy for rigid semiconducting substrates was devised. Architectures for comprehensively compliant semiconductors were created as a result. Si and GaN-on-Si have been segmented into both highly flexible and rigid segments. An advanced controlled cleavage technique has been integrated into the manufacturing process. The bending radius of the substrate has been decoupled from the substrate thickness thus allowing for higher mechanical stability, while achieving bending radii below 250 .m. Novel fabrication workflows have been created, one of which is completely compatible with CMOS fabrication techniques, while still being cost effective. Each of the rigid segments have been designed to carry in excess of its own weight. The reliability of the interconnecting springs was examined by rugged cyclic bending and twisting tests. Finite element simulations in COMSOL exhibited no stress for the rigid segments. For the first time a flexible and/or stretchable Si substrate has been integrated with pick and place tool technology. Additionally the platform serves as a More-than-Moore technology, by folding the monocrystalline substrate on top of itself, while routing power through the flexible segments. This More-than-Moore (MtM) technology has the advantages of System-in-Package (SiP) but does not have the additional costs. From this compliant approach a qubic 4D electronic platform was created. An aerially deployable electronic system was achieved by incorporating thermal paste into the qubic platform. Energy storage, sensing, and actuating were successfully tested on the system. Buried cavities for microfluidics were developed for on-chip chemical and biological processes. A platform was developed for µTF-SOFCs deposition. Cavities were interconnected subterraneously and columnar anodes were developed to enhance the fuel flow in the fuel cell electrode. The triple phase boundary (TPB) was enhanced by over an order of magnitude in comparison to standard processing techniques. A subsequent, microfluidic platform was developed for biological applications. The wettability of the platform gave good results for water, as well as for neurobasal media buffer. Tests indicate that neurons can grow directly on the platform.

This thesis reports the fabrication of three dimensionally independent on-chip microchannels using a CMOS-compatible single mask deep reactive ion etching (DRIE) process for cooling 3D ICs. Three dimensionally independent microchannels are fabricated by utilizing the RIE lag effect. This allows complex microchannel configurations to be fabricated using a single mask and single silicon etch step. Furthermore, the microchannels are sealed in one step by low temperature oxide deposition. The micro-fin channels heat transfer characteristics are similar to previously published channel designs by being capable of removing 185 W/cm2 before the junction temperatures active elements exceed 85°C. To examine the heat transfer characteristics of this proposed on-chip cooler, different channel geometries were simulated using computational fluid dynamics. The channel designs were simulated using 20°C water at different flow rates to achieve a laminar flow regime with Reynolds numbers ranging from 200 to 500. The steady state simulations were performed using a heat flux of 100 W/cm2. Simulation results were verified using fabricated test chips. A micro-fin geometry showed to have the highest heat transfer capability and lowest simulated substrate temperatures. While operating with a Reynolds number of 400, a Nusselt number per input energy (Nu/Q) of 0.24 W-1 was achieved. The micro-fin geometry is also capable of cooling a substrate with a heat flux of 100W/cm2 to 45ºC with a Reynolds number of 525. These channels also have a lower thermal resistance compared to external heat sinks because there is no heat spreader or thermal interface material layer. / Master of Science

The Photonic Crystal (PC) is a potential candidate for a compact optical integrated circuit on a solid state platform. The fabrication process of a PC is compatible with CMOS technology; thus, it could be potentially employed in hybrid optical and electrical integrated circuits. One of the main obstacles in the implementation of an integrated optical circuit is the polarization dependence of wave propagation. Our goal is to overcome this obstacle by implementing PC based polarization controlling devices. One of the crucial elements of polarization controlling devices is the polarization rotator. The polarization rotator is utilized to manipulate and rotate the polarization of light. In this thesis, we have proposed, designed and implemented an ultra-compact passive PC based polarization rotator. Passive polarization rotator structures are mostly composed of geometrically asymmetric structures. The polarization rotator structure consists of a single defect line PC slab waveguide. The geometrical asymmetry has been introduced on top of the defect line as an asymmetric loaded layer. The top loaded layer is asymmetric with respect to the z-axis propagation direction. To synchronize the power conversion and avoid power conversion reversal, the top loaded layer is alternated around the z-axis periodically. The structure is called periodic asymmetric loaded PC slab waveguide. Due to the compactness of the proposed structure, a rigorous numerical method, 3D-FDTD can be employed to analyze and simulate the final designed structure. For the quick preliminary design, an analytical method that provides good approximate values of the structural parameters is preferred. Coupled-mode theory is a robust and well-known method for such analyses of perturbed waveguide structures. Thus, a coupled-mode theory based on semi-vectorial modes was developed for propagation modeling on square hole PC structures. In essence, we wish to develop a simple yet closed form method to carry out the initial design of the device of interest. In the next step, we refined the design by using rigorous but numerically expensive 3D-FDTD simulations. We believe this approach leads to optimization of the device parameters easily, if desired. To extend the design to a more general shape PC based polarization rotator, a design methodology based on hybrid modes of asymmetric loaded PC slab waveguide was introduced. The hybrid modes of the structure were calculated utilizing the 3D-FDTD method combined with the Spatial Fourier Transform (SFT). The propagation constants and profile of the slow and fast modes of an asymmetric loaded PC slab waveguide were extracted from the 3D-FDTD simulation results. The half-beat length, which is the length of each loaded layer, and total number of the loaded layers are calculated using the aforementioned data. This method provides the exact values of the polarization rotator structure’s parameter. The square hole PC based polarization rotator was designed employing both coupled-mode theory and normal modal analysis for THz frequency applications. Both design methods led to the same results. The design was verified by the 3D-FDTD simulation of the polarization rotator structure. For a square hole PC polarization rotator, a polarization conversion efficiency higher than 90% over the propagation distance of 12 λ was achieved within the frequency band of 586.4-604.5 GHz corresponding to the normalized frequency of 0.258-0.267. The design was extended to a circular hole PC based polarization rotator. A polarization conversion efficiency higher than 75% was achieved within the frequency band of 600-604.5 GHz. The circular hole PC polarization rotator is more compact than the square-hole PC structure. On the other hand, the circular hole PC polarization rotator is narrow band in comparison with the square hole PC polarization rotator. In a circular hole PC slab structure, the Bloch modes (fast and slow modes) couple energy to the TM-like PC slab modes. In both square and circular hole PC slab structures with finite number of rows, and the TM-like PC slab modes are extended to the lower edge of the bandgap. In bandgap calculation using PWEM, it is assumed that the PC structure is extended to infinity, however in practice the number of rows is limited, which is the source of discrepancy between the bandgap calculation using PWEM and 3D-FDTD. In an asymmetric loaded circular hole PC slab waveguide, the leaky TM-like PC slab modes are extended deep inside the bandgap and overlapped with both the slow and fast Bloch modes; whereas, in an asymmetric loaded square hole PC slab waveguide, the leaky TM-like PC slab modes are below the frequency band of slow and fast modes. Therefore, TM-like PC slab modes have significantly more adverse effect on the performance of the circular-hole based polarization rotator leading to a narrow band structure. SOI based PC membrane technology for THz application was developed. The device layer is made of highly resistive silicon to maintain low loss propagation for THz wave. The PC slab waveguide and polarization rotators were fabricated employing this technology. Finally, an a-SiON PC slab waveguide structures were also fabricated at low temperature for optical applications. This technology has the potential to be implemented on any substrate or CMOS chips.

The Photonic Crystal (PC) is a potential candidate for a compact optical integrated circuit on a solid state platform. The fabrication process of a PC is compatible with CMOS technology; thus, it could be potentially employed in hybrid optical and electrical integrated circuits. One of the main obstacles in the implementation of an integrated optical circuit is the polarization dependence of wave propagation. Our goal is to overcome this obstacle by implementing PC based polarization controlling devices. One of the crucial elements of polarization controlling devices is the polarization rotator. The polarization rotator is utilized to manipulate and rotate the polarization of light. In this thesis, we have proposed, designed and implemented an ultra-compact passive PC based polarization rotator. Passive polarization rotator structures are mostly composed of geometrically asymmetric structures. The polarization rotator structure consists of a single defect line PC slab waveguide. The geometrical asymmetry has been introduced on top of the defect line as an asymmetric loaded layer. The top loaded layer is asymmetric with respect to the z-axis propagation direction. To synchronize the power conversion and avoid power conversion reversal, the top loaded layer is alternated around the z-axis periodically. The structure is called periodic asymmetric loaded PC slab waveguide. Due to the compactness of the proposed structure, a rigorous numerical method, 3D-FDTD can be employed to analyze and simulate the final designed structure. For the quick preliminary design, an analytical method that provides good approximate values of the structural parameters is preferred. Coupled-mode theory is a robust and well-known method for such analyses of perturbed waveguide structures. Thus, a coupled-mode theory based on semi-vectorial modes was developed for propagation modeling on square hole PC structures. In essence, we wish to develop a simple yet closed form method to carry out the initial design of the device of interest. In the next step, we refined the design by using rigorous but numerically expensive 3D-FDTD simulations. We believe this approach leads to optimization of the device parameters easily, if desired. To extend the design to a more general shape PC based polarization rotator, a design methodology based on hybrid modes of asymmetric loaded PC slab waveguide was introduced. The hybrid modes of the structure were calculated utilizing the 3D-FDTD method combined with the Spatial Fourier Transform (SFT). The propagation constants and profile of the slow and fast modes of an asymmetric loaded PC slab waveguide were extracted from the 3D-FDTD simulation results. The half-beat length, which is the length of each loaded layer, and total number of the loaded layers are calculated using the aforementioned data. This method provides the exact values of the polarization rotator structure’s parameter. The square hole PC based polarization rotator was designed employing both coupled-mode theory and normal modal analysis for THz frequency applications. Both design methods led to the same results. The design was verified by the 3D-FDTD simulation of the polarization rotator structure. For a square hole PC polarization rotator, a polarization conversion efficiency higher than 90% over the propagation distance of 12 λ was achieved within the frequency band of 586.4-604.5 GHz corresponding to the normalized frequency of 0.258-0.267. The design was extended to a circular hole PC based polarization rotator. A polarization conversion efficiency higher than 75% was achieved within the frequency band of 600-604.5 GHz. The circular hole PC polarization rotator is more compact than the square-hole PC structure. On the other hand, the circular hole PC polarization rotator is narrow band in comparison with the square hole PC polarization rotator. In a circular hole PC slab structure, the Bloch modes (fast and slow modes) couple energy to the TM-like PC slab modes. In both square and circular hole PC slab structures with finite number of rows, and the TM-like PC slab modes are extended to the lower edge of the bandgap. In bandgap calculation using PWEM, it is assumed that the PC structure is extended to infinity, however in practice the number of rows is limited, which is the source of discrepancy between the bandgap calculation using PWEM and 3D-FDTD. In an asymmetric loaded circular hole PC slab waveguide, the leaky TM-like PC slab modes are extended deep inside the bandgap and overlapped with both the slow and fast Bloch modes; whereas, in an asymmetric loaded square hole PC slab waveguide, the leaky TM-like PC slab modes are below the frequency band of slow and fast modes. Therefore, TM-like PC slab modes have significantly more adverse effect on the performance of the circular-hole based polarization rotator leading to a narrow band structure. SOI based PC membrane technology for THz application was developed. The device layer is made of highly resistive silicon to maintain low loss propagation for THz wave. The PC slab waveguide and polarization rotators were fabricated employing this technology. Finally, an a-SiON PC slab waveguide structures were also fabricated at low temperature for optical applications. This technology has the potential to be implemented on any substrate or CMOS chips.

A fully integrated optical chem/bio sensor complete with integrated source, chemically sensitive waveguide, detector arrays, and associated signal processing electronics on a Si-CMOS chip is a challenging, but highly desirable goal. An evanescent-wave multimode interferometric sensing element is a sensitive method for sensing, which is easily integrated on Si-CMOS. This work is concerned with the design, analysis, and demonstration of a planar multimode interferometric chem/bio sensor that is compatible with the fabrication constraints of Si-CMOS. A 4000-micron-long interferometric that can be adapted for different agents by a particular sensing layer has been fabricated on silicon using silicon dioxide and silicon oxynitride. Hexaflouro-isopropanol substituted polynorbornene is the sensing layer. This sensor has also been fabricated on a Si-CMOS circuit with embedded photodetectors. A sensor on silicon was demonstrated with a minimum detectable index change of 2.0x10-6 using an accurate gas delivery system and a custom hermetic waveguide test chamber. A modal pattern analysis strategy has also been developed to extract the optimal SNR from the measured modal patterns. An understanding of the noise processes and spatial bandwidth effects has enabled an experimentally-based prediction of the index sensitivity of a fully integrated multimode chem/bio sensor on Si-CMOS at 9.2 x10-7. Theoretically, the sensitivity enhancement of high over low index sensing layers and transverse-magnetic over transverse electric modes is described. Also, the sensitivity enhancement of higher-order-transverse modes has been quantified. The wide-angle beam propagation method has been used to simulate the sensor. This simulation showed the relation between the modal pattern repetition period and sensor sensitivity. Further, the modal coupling properties of the multimode y-junction have been described. A second multimode y-junction has been designed to change the modal excitation under the SL, and thus the sensitivity. The chemo-optic response of the `substituted polynorbornene' polymer., hexaflouro-isopropanol substituted polynorbornene to methanol, water, iso-propanol, and benzene has been measured. Also, its thermo-optic response has been measured. Athermal interferometric chem/bio sensors have then been suggested.

A novel fabrication process is presented which allows for three-dimensionally independent features to be etched in silicon using SF6 gas in a deep reactive ion etcher (DRIE) after a single etch step. The mechanism allowing for different feature depths and widths to be produced over a wafer is reactive ion etch lag, where etch rate scales with the exposed feature size in the mask. A modified Langmuir model has been developed relating the geometry of the exposed areas in a specific mask pattern as well as the etch duration to the final depth and width of a channel that is produced after isotropic silicon etching. This fabrication process is tailored for microfluidic network design, but the capabilities of the process can be applied elsewhere. A characterization of an Alcatel DRIE tool is also presented in order to enhance RIE lag by varying etch process parameters, increasing the variety of channel sizes that can be fabricated. High values of flow rate, coil power, and pressure were found to produce this effect. The capability of the modeled process for creating a microchip cooling device for high-heat flux applications was also investigated. Using meander channels, heat flux in excess of 100W/cm2 were cooled using 750µL/s flow rate of water through the chip. This single-mask process reduces risk of damage to the chip and provides the capability to cool high-heat-flux microprocessors for the next 10 years, and for an even longer time once the geometry of the channels is optimized. / Master of Science

This thesis reports on a new implementation of high quality factor (Q) copper (Cu) inductors on CMOS-grade (10-20ohm.cm) silicon (Si) substrates using a fully CMOS-compatible process. A low-temperature (less than300C) fabrication sequence is employed to reduce the loss of Si wafers at RF frequencies by trenching the Si substrate. The high aspect-ratio (30:1) trenches are subsequently bridged over or refilled with a low-loss material to close the open areas and to create a rigid low-loss island (Trenched Si Island) on which the inductors can be fabricated. The method reported here does not require air suspension of the inductors, resulting in mechanically-robust structures that are compatible with any packaging technology. The metal loss of inductors is reduced by electroplating thick (~20m) Cu layer. Fabricated inductors are characterized and modeled from S-parameter measurement. Measurement results are in good agreement with SONNET electromagnetic simulations. A one-turn 0.8nH Cu inductor fabricated on a Trenched Silicon Island (TSI) exhibits high Q of 71 at 8.75 GHz. Whereas, the identical inductor fabricated on a 20um thick silicon dioxide (SiO2) coated standard Si substrate has a maximum Q of 41 at 1.95GHz. Comparing the Q of inductors on TSI with that of other micromachined Si substrates reveals the significant effect of trenching the Si in reduction of the substrate loss. This thesis outlines the design, fabrication, characterization and modeling of spiral type Cu inductors on the TSIs.

<p>Semiconductor wafer bonding has been a subject of interestfor many years and a wide variety of wafer bonding techniqueshave been reported in literature. In adhesive wafer bondingorganic and inorganic adhesives are used as intermediatebonding material. The main advantages of adhesive wafer bondingare the relatively low bonding temperatures, the lack of needfor an electric voltage or current, the compatibility withstandard CMOS wafers and the ability to join practically anykind of wafer materials. Adhesive wafer bonding requires nospecial wafer surface treatmentssuch as planarisation.Structures and particles at the wafer surfaces can be toleratedand compensated for some extent by the adhesive material.Adhesive wafer bonding is a comparably simple, robust andlowcost bonding process. In this thesis, adhesive wafer bondingtechniques with different polymer adhesives have beendeveloped. The relevant bonding parameters needed to achievehigh quality and high yield wafer bonds have been investigated.A selective adhesive wafer bonding process has also beendeveloped that allows localised bonding on lithographicallydefined wafer areas.</p><p>Adhesive wafer bonding has been utilised in variousapplication areas. A novel CMOS compatible film, device andmembrane transfer bonding technique has been developed. Thistechnique allows the integration of standard CMOS circuits withthin film transducers that can consist of practically any typeof crystalline or noncrystalline high performance material(e.g. monocrystalline silicon, gallium arsenide,indium-phosphide, etc.). The transferred transducers or filmscan be thinner than 0.3 µm. The feature sizes of thetransferred transducers can be below 1.5 µm and theelectrical via contacts between the transducers and the newsubstrate wafer can be as small as 3x3 µm2. Teststructures for temperature coefficient of resistancemeasurements of semiconductor materials have been fabricatedusing device transfer bonding. Arrays of polycrystallinesilicon bolometers for use in uncooled infrared focal planearrays have been fabricated using membrane transfer bonding.The bolometers consist of free-hanging membrane structures thatare thermally isolated from the substrate wafer. Thepolycrystalline silicon bolometers are fabricated on asacrificial substrate wafer. Subsequently, they are transferredand integrated on a new substrate wafer using membrane transferbonding. With the same membrane transfer bonding technique,arrays of torsional monocrystalline silicon micromirrors havebeen fabricated. The mirrors have a size of 16x16 µm2 anda thickness of 0.34 µm. The advantages of micromirrorsmade of monocrystalline silicon are their flatness, uniformityand mechanical stability. Selective adhesive wafer bonding hasbeen used to fabricate very shallow cavities that can beutilised in packaging and component protection applications. Anew concept is proposed that allows hermetic sealing ofcavities fabricated using adhesive wafer bonding. Furthermore,microfluidic devices, channels and passive valves for use inmicro total analysis systems are presented.</p><p>Adhesive wafer bonding is a generic CMOS compatible bondingtechnique that can be used for fabrication and integration ofvarious microsystems such as infrared focal plane arrays,spatial light modulators, microoptical systems, laser systems,MEMS, RF-MEMS and stacking of active electronic films forthree-dimensional high-density integration of electroniccircuits. Adhesive wafer bonding can also be used forfabrication of microcavities in packaging applications, forwafer-level stacking of integrated circuit chips (e.g. memorychips) and for fabrication of microfluidic systems.</p>

The international technology roadmap for semiconductors (ITRS) 2012 report foresees the use of porous dielectric materials with a low dielectric constant in conjunction with copper interconnects as a way to reduce the resistive-capacitive (RC) delay in microelectronic applications. However, the introduction of pores in the dielectric not only serves as stress raisers but also diminishes the structural strength of the material. The challenge therefore with the implementation of low-k dielectrics for high-performance flip-chip packages is to create a reliable die to organic substrate interconnect solution which induces low stresses on the die to prevent the cohesive cracking and the interfacial delamination of the dielectric material. Potential interconnect solutions that meet this challenge are MEMS-like compliant freestanding micro-structures. These structures are designed to work as spring-like elements which allow the free lateral and out-of-plane motion between the silicon die and the organic substrate under assembly conditions as well as under thermal or power cycling. Thus, the focus of this research is to design, fabricate, and characterize electrically and mechanically an innovative compliant interconnect approach that addresses these challenges. The proposed interconnect is scalable in dimensions and pitch, and consists multiple electrical paths which will provide redundancy against interconnect failure. The multi-path design employs parallel electrical paths which effectively split a larger cross-sectional area into several smaller areas making the overall design more compliant than otherwise. This research proposes wafer-level, high-yield, CMOS-compatible fabrication procedure using sequential photolithography and copper electroplating. The proposed interconnects are symmetric and are amenable to easy reflow assembly to substrates. The mechanical compliance of the fabricated structures is studied through nano-indentation, while the electrical characteristics are assessed through fabricated prototypes. The xvi thermo-mechanical reliability of compliant interconnects is also demonstrated. Lastly, the dimensional scalability of the interconnects is also demonstrated.

Semiconductor wafer bonding has been a subject of interestfor many years and a wide variety of wafer bonding techniqueshave been reported in literature. In adhesive wafer bondingorganic and inorganic adhesives are used as intermediatebonding material. The main advantages of adhesive wafer bondingare the relatively low bonding temperatures, the lack of needfor an electric voltage or current, the compatibility withstandard CMOS wafers and the ability to join practically anykind of wafer materials. Adhesive wafer bonding requires nospecial wafer surface treatmentssuch as planarisation.Structures and particles at the wafer surfaces can be toleratedand compensated for some extent by the adhesive material.Adhesive wafer bonding is a comparably simple, robust andlowcost bonding process. In this thesis, adhesive wafer bondingtechniques with different polymer adhesives have beendeveloped. The relevant bonding parameters needed to achievehigh quality and high yield wafer bonds have been investigated.A selective adhesive wafer bonding process has also beendeveloped that allows localised bonding on lithographicallydefined wafer areas. Adhesive wafer bonding has been utilised in variousapplication areas. A novel CMOS compatible film, device andmembrane transfer bonding technique has been developed. Thistechnique allows the integration of standard CMOS circuits withthin film transducers that can consist of practically any typeof crystalline or noncrystalline high performance material(e.g. monocrystalline silicon, gallium arsenide,indium-phosphide, etc.). The transferred transducers or filmscan be thinner than 0.3 µm. The feature sizes of thetransferred transducers can be below 1.5 µm and theelectrical via contacts between the transducers and the newsubstrate wafer can be as small as 3x3 µm2. Teststructures for temperature coefficient of resistancemeasurements of semiconductor materials have been fabricatedusing device transfer bonding. Arrays of polycrystallinesilicon bolometers for use in uncooled infrared focal planearrays have been fabricated using membrane transfer bonding.The bolometers consist of free-hanging membrane structures thatare thermally isolated from the substrate wafer. Thepolycrystalline silicon bolometers are fabricated on asacrificial substrate wafer. Subsequently, they are transferredand integrated on a new substrate wafer using membrane transferbonding. With the same membrane transfer bonding technique,arrays of torsional monocrystalline silicon micromirrors havebeen fabricated. The mirrors have a size of 16x16 µm2 anda thickness of 0.34 µm. The advantages of micromirrorsmade of monocrystalline silicon are their flatness, uniformityand mechanical stability. Selective adhesive wafer bonding hasbeen used to fabricate very shallow cavities that can beutilised in packaging and component protection applications. Anew concept is proposed that allows hermetic sealing ofcavities fabricated using adhesive wafer bonding. Furthermore,microfluidic devices, channels and passive valves for use inmicro total analysis systems are presented. Adhesive wafer bonding is a generic CMOS compatible bondingtechnique that can be used for fabrication and integration ofvarious microsystems such as infrared focal plane arrays,spatial light modulators, microoptical systems, laser systems,MEMS, RF-MEMS and stacking of active electronic films forthree-dimensional high-density integration of electroniccircuits. Adhesive wafer bonding can also be used forfabrication of microcavities in packaging applications, forwafer-level stacking of integrated circuit chips (e.g. memorychips) and for fabrication of microfluidic systems.