A novel method of current sensing using resistance of power delivery path is introduced as a mean to measure static or dynamic load current in high-power system-on-chips, where conventional methods deemed inadequate. It is named ???IRS??? here, and it stands for Inherent Resistance Current Sensing. To explain its application and to provide motivation beyond this work, pros and cons of conventional techniques are reviewed with a look at previous works done in this area. It is followed with review of discreet implementation of the sensor (IRS) in chapter three. The measurements results collected using the discrete circuits are included with an in-depth analysis of the results and compensation techniques. It offers insight to effectiveness of the solution and its potential, while highlighting shortcomings and limitation of discrete implementation. This would set the tone to design integrated version of the sensor. In order to select amplifier architecture, a rundown of common methods to construct the instrumentation amplifier is discussed in chapter 4, primarily based on the latest work already done in this field per cited references. This is to help readers to get an overall view of the challenges and techniques to overcome them. Finally, the architecture for the integrated version of the sensor (IRS) is presented, with a proof of concept design. The design is targeted for low voltage VLSI systems to allow integration within large SoCs such as GPUs and CPUs. The primary block, the instrumentation amplifier, is constructed using rail-to-rail current conveyers and simulated using TSMC 32nm process node. The simulation results are analyzed and observations are provided.

abstract: The growing demand for high performance and power hungry portable electronic devices has resulted in alarmingly serious thermal concerns in recent times. The power management system of such devices has thus become increasingly more vital. An integral component of this system is a Low-Dropout Regulator (LDO) which inherently generates a low-noise power supply. Such power supplies are crucial for noise sensitive analog blocks like analog-to-digital converters, phase locked loops, radio-frequency circuits, etc. At higher output power however, a single LDO suffers from increased heat dissipation leading to thermal issues. This research presents a novel approach to equally and accurately share a large output load current across multiple parallel LDOs to spread the dissipated heat uniformly. The proposed techniques to achieve a high load sharing accuracy of 1% include an innovative fully-integrated accurate current sensing technique based on Dynamic Element Matching and an integrator based servo loop with a low offset feedback amplifier. A novel compensation scheme based on a switched capacitor resistor is referenced to address the high 2A output current specification per LDO across an output voltage range of 1V to 3V. The presented scheme also reduces stringent requirements on off-chip board traces and number of off-chip components thereby making it suitable for portable hand-held systems. The proposed approach can theoretically be extended to any number of parallel LDOs increasing the output current range extensively. The designed load sharing LDO features fast transient response for a low quiescent current consumption of 300µA with a power-supply rejection of 60.7dB at DC. The proposed load sharing technique is verified through extensive simulations for various sources and ranges of mismatch across process, voltage and temperature. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

A novel method of current sensing using resistance of power delivery path is introduced as a mean to measure static or dynamic load current in high-power system-on-chips, where conventional methods deemed inadequate. It is named “IRS” here, and it stands for Inherent Resistance Current Sensing. To explain its application and to provide motivation beyond this work, pros and cons of conventional techniques are reviewed with a look at previous works done in this area. It is followed with review of discreet implementation of the sensor (IRS) in chapter three. The measurements results collected using the discrete circuits are included with an in-depth analysis of the results and compensation techniques. It offers insight to effectiveness of the solution and its potential, while highlighting shortcomings and limitation of discrete implementation. This would set the tone to design integrated version of the sensor. In order to select amplifier architecture, a rundown of common methods to construct the instrumentation amplifier is discussed in chapter 4, primarily based on the latest work already done in this field per cited references. This is to help readers to get an overall view of the challenges and techniques to overcome them. Finally, the architecture for the integrated version of the sensor (IRS) is presented, with a proof of concept design. The design is targeted for low voltage VLSI systems to allow integration within large SoCs such as GPUs and CPUs. The primary block, the instrumentation amplifier, is constructed using rail-to-rail current conveyers and simulated using TSMC 32nm process node. The simulation results are analyzed and observations are provided.

Global on-chip interconnects in deep sub-micron CMOS present challenges in satisfying delay constraints in the presence of noise and dramatic temperature variations, while minimizing energy consumption due to leakage and static power. Although repeaters are typically used to reduce delay and maintain signal integrity in long interconnects, they introduce significant area, power (both dynamic and leakage), delay, noise and design overhead as well as exacerbating variations due to their local power supply noise and temperature. Current-Sensing is an alternative to repeaters that transfers signals with no intermediate circuits by sensing current rather than voltage at the end of a long interconnect. Among the current sensing circuits, Differential Current-Sensing (DCS), which uses conventional CMOS inverters to drive differential signal, is preferred because of its high common-mode noise rejection. The DCS circuit is fast and simple in layout compared to repeater insertion despite significant static and leakage power which remains a barrier for broad application. Temperature variation throughout the chip also causes the timing uncertainty on interconnects to increase. This thesis addresses current-sensing interconnect circuit design in several aspects. First, it provides an improved differential current-sensing circuit called the differential leakage-aware sense amplifier (DLASA), that uses local power gating that results in 39.6% reduced leakage and static power compared to conventional differential current sensing. Secondly, thermal impact on interconnect is studied and temperature sensitivity is analyzed for interconnect circuits. Theoretical analysis is discussed as a base design guideline, then accurate simulation based experiments in 65nm, 45nm and 32nm CMOS technologies are used for verification from 25OC to 150OC. Thus this project provides a view of the year of technology toward 2013.

Closed loop Hall-effect current sensors used in power electronic applications require high bandwidth and small transient errors. For this, the behaviour of a closed loop Hall-e ect current sensor is modeled. Analytical expression of the step response of the sensor using this model is used to evaluate the performance of the PI compensator in the current sensor. Based on this expression a procedure is proposed to design parameters of the PI compensator for fast dynamic performance and for small transient error. A prototype closed loop Hall-effect current sensor is built in the laboratory. A PI compensator based on the procedure devised earlier is designed for the sensor. A power electronic converter based current source is designed and fabricated in the labo-ratory for validation of steady state and transient performance of Hall-effect current sensors. A novel hardware topology is proposed, using which the same hardware set-up can produce both step current and sinusoidal current in its designated sections without any modi cation in the hardware con guration. It produces step current of controlled peak value upto 100A and controlled rate of change with both positive and negative dtdi . The step transition time is less than 200ns. The dtdi is adjustable upto a limit of 300A/ s to verify the dtdi following capability of the sensor. The same current source produces continuous sinusoidal current of controlled magnitude upto 75A peak and controlled frequency from 1Hz to 1000Hz. The magnitude and the frequency of the sinusoidal current can be varied on-line like a voltage function generator. The hardware of the current source is designed to consume minimal ac-tive power from mains during continuous sinusoidal current generation. This current source is used in experimental veri cation of the steady state and the transient performance of the designed laboratory current sensor. The transient performance of the laboratory current sensor is observed to be superior to state-of-the-art commercial current sensors available for power electronic applications.

This dissertation presents the concept of a small, low-cost, self-powered smart wireless sensor that can be used for monitoring current, temperature and voltage on a variety of utility assets. Novel energy harvesting approaches are proposed that enable the sensor to operate without batteries and to have an expected life of 20-30 years. The sensor measures current flowing in an asset using an open ferromagnetic core, unlike a CT which uses a closed core, which makes the proposed sensor small in size, and low-cost. Further, it allows the sensor to operate in conjunction with different assets having different geometries, such as bus-bars, cables, disconnect switches, overhead conductors, transformers, and shunt capacitors, and function even when kept in the vicinity of an asset. Two novel current sensing algorithms have been developed that help the sensor to autonomously calibrate and make the sensor immune from far-fields and cross-talk. The current sensing algorithms have been implemented and tested in the lab at up to 1000 A. This research also presents a novel self-calibrating low-cost voltage sensing technique. The major purpose of voltage sensing is detection of sags, swells and loss-ofpower on the asset; therefore, the constraint on error in measurement is relaxed. The technique has been tested through several simulation studies. A voltage sensor prototype has been developed and tested on a high voltage bus at up to 35 kV. Finally, a study of sensor operation under faults, such as lightning strikes, and large short circuit currents has been presented. These studies are conducted using simulations and actual experiments. Based on the results of the experiments, a robust protection circuit for the sensor is proposed. Issues related to corona and external electrical noise on the communication network are also discussed and experimentally tested. Further, optimal design of the energy harvester and a novel design of package for the sensor that prevents the circuitry from external electrical noise without attenuation of power signals for the energy harvester are also proposed.

Switching power converters are an indispensable part of every battery-operated consumer electronic product, nourishing regulated voltages to various subsystems. In these circuits, sensing the inductor current is not only necessary for protection and control but also is critical to be done in a lossless and accurate fashion for state-of-the-art advanced control techniques, which are devised to optimize transient response, increase the efficiency over a wide range of loads, eliminate off-chip compensation networks, and integrate the power inductor. However, unavailability of a universal, integrable, lossless, and accurate current-sensing technique impedes the realization of those advanced techniques and limit their applications. Unfortunately, use of a conventional series sense resistor is not recommended in high-performance, high-power switching regulators where more than 90% efficiency is required because of their high current levels. A handful of lossless current-sensing techniques are available but their accuracies are significantly lower than the traditional sense resistor scheme. Among available lossless but not accurate techniques, an off-chip, filter-based method that uses a tuned filter across the inductor to estimate current flow and its accuracy is dependent on the inductance and its equivalent series resistance (ESR) was selected for improvement because of its inherent continuous and low-noise operation. A schemes is proposed to adapt the filter technique for integration by automatically adjusting bandwidth and gain of an on-chip programmable gm-C filter to the off-chip power inductor during the system start-up through measuring the inductance and its ESR with on-chip generated test currents. The IC prototype in AMI s 0.5-um CMOS process achieved overall DC and AC gain errors of 8% and 9%, respectively, at 0.8 A DC load and 0.2 A ripple currents for inductors from 4 uH-14 uH and ESR from 48 mOhm to 384 mOhm when lossless, state-of-the-art schemes achieve 20 40% error and only when the nominal specifications of power component (power MOSFET or inductor) are known. Moreover, the proposed circuit improved the efficiency of a test bed current-mode controlled switching regulator by more than 2.6% at 0.8 A load compared to the traditional sense resistor technique with a 50 mOhm sense resistor.

Power consumption is the primary concern in battery-operated portable applications. Buck converters have gained popularity in powering portable devices due to their compact size, good current delivery capability and high efficiency. However, portable devices are operating under light load condition for the most of the time. Conventional buck converters suffer from low light-load efficiency which severely limits battery lifetime. In this project, a novel technique for buck converter is proposed to reduce the switching loss by reducing the effective input supply voltage at light load. This is achieved by switching between two different input voltages (3.3V and 1.65V) depending on the output current value. Experimental results show that this technique improves the efficiency at light loads by 18.07%. The buck voltage possesses an output voltage of 0.9V and provides a maximum output current of 400mA. The buck converter operates at a switching frequency of 1MHz. The prototype was fabricated using 0.18µm CMOS technology, and occupies a total active area of 0.6039mm^2.

abstract: Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC-DC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power monitoring. Current Shunt Monitor (CSM) systems have various applications for precise current monitoring of those aforementioned applications. CSMs enable current measurement across an external sense resistor (RS) in series to current flow. Two different types of CSMs designed and characterized in this paper. First design used direct current reading method and the other design used indirect current reading method. Proposed CSM systems can sense power supply current ranging from 1mA to 200mA for the direct current reading topology and from 1mA to 500mA for the indirect current reading topology across a typical board Cu-trace resistance of 1 ohm with less than 10 µV input-referred offset, 0.3 µV/°C offset drift and 0.1% accuracy for both topologies. Proposed systems avoid using a costly zero-temperature coefficient (TC) sense resistor that is normally used in typical CSM systems. Instead, both of the designs used existing Cu-trace on the printed circuit board (PCB) in place of the costly resistor. The systems use chopper stabilization at the front-end amplifier signal path to suppress input-referred offset down to less than 10 µV. Switching current-mode (SI) FIR filtering technique is used at the instrumentation amplifier output to filter out the chopping ripple caused by input offset and flicker noise by averaging half of the phase 1 signal and the other half of the phase 2 signal. In addition, residual offset mainly caused by clock feed-through and charge injection of the chopper switches at the chopping frequency and its multiple frequencies notched out by the since response of the SI-FIR filter. A frequency domain Sigma Delta ADC which is used for the indirect current reading type design enables a digital interface to processor applications with minimally added circuitries to build a simple 1st order Sigma Delta ADC. The CSMs are fabricated on a 0.7µm CMOS process with 3 levels of metal, with maximum Vds tolerance of 8V and operates across a common mode range of 0 to 26V for the direct current reading type and of 0 to 30V for the indirect current reading type achieving less than 10nV/sqrtHz of flicker noise at 100 Hz for both approaches. By using a semi-digital SI-FIR filter, residual chopper offset is suppressed down to 0.5mVpp from a baseline of 8mVpp, which is equivalent to 25dB suppression. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

abstract: Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for current sensing such as external resistor sensing, triode mode current mirroring, observer sensing, Hall-Effect sensors, transformers, DC Resistance (DCR) sensing, Gm-C filter sensing etc. However, each method has one or more issues that prevent them from being successfully applied in DC-DC converter, e.g. low accuracy, discontinuous sensing nature, high sensitivity to switching noise, high cost, requirement of known external power filter components, bulky size, etc. In this dissertation, an offset-independent inductor Built-In Self Test (BIST) architecture is proposed which is able to measure the inductor inductance and DCR. The measured DCR enables the proposed continuous, lossless, average current sensing scheme. A digital Voltage Mode Control (VMC) DC-DC buck converter with the inductor BIST and current sensing architecture is designed, fabricated, and experimentally tested. The average measurement errors for inductance, DCR and current sensing are 2.1%, 3.6%, and 1.5% respectively. For the 3.5mm by 3.5mm die area, inductor BIST and current sensing circuits including related pins only consume 5.2% of the die area. BIST mode draws 40mA current for a maximum time period of 200us upon start-up and the continuous current sensing consumes about 400uA quiescent current. This buck converter utilizes an adaptive compensator. It could update compensator internally so that the overall system has a proper loop response for large range inductance and load current. Next, a digital Average Current Mode Control (ACMC) DC-DC buck converter with the proposed average current sensing circuits is designed and tested. To reduce chip area and power consumption, a 9 bits hybrid Digital Pulse Width Modulator (DPWM) which uses a Mixed-mode DLL (MDLL) is also proposed. The DC-DC converter has a maximum of 12V input, 1-11 V output range, and a maximum of 3W output power. The maximum error of one least significant bit (LSB) delay of the proposed DPWM is less than 1%. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011