Technology scaling trends lead to shrinking of the individual elements like transistors and wires in digital systems. The main driving force behind this is cutting the cost of the systems while the systems are filled with extra functionalities. This is the reason why a 3 GHz Intel processor now is priced less than what a 50MHz processor was priced 10 years ago. As in most cases, this comes with a price. This price is the complex design process and problems that stem from the reduction in physical dimensions. As the transistors became smaller in size and the systems became faster, issues like power consumption, signal integrity, soft error tolerance, and testing became serious challenges. There is an increasing demand to put CAD tools in the design flow to address these issues at every step of the design process. First part of this research investigates circuit level techniques to reduce power consumption in digital systems. In second part, improving soft error tolerance of digital systems is considered as a trade off problem between power and reliability and a power aware dynamic soft error tolerance control strategy is developed. The objective of this research is to provide CAD tools and circuit design techniques to optimize power consumption and to increase soft error tolerance of digital circuits. Multiple supply and threshold voltages are used to reduce power consumption. Variable supply and threshold voltages are used together with variable capacitances to develop a dynamic soft error tolerance control scheme.

Power consumption and device size have been placed at the primary concerns for battery-operated portable applications. Switching converters gain popularity in powering portable devices due to their high efficiency, compact sizes and high current delivery capability. However portable devices usually operate at light loads most of the time and are only required to deliver high current in very short periods, while conventional buck converter suffers from low efficiency at light load due to the switching losses that do not scale with load current. In this research, a novel technique for buck converter is proposed to reduce the switching loss by reducing the effective voltage supply at light load. This buck converter, implemented in TSMC 0.18 micrometers CMOS technology, operates with a input voltage of 3.3V and generates an output voltage of 0.9V, delivers a load current from 1mA to 400mA, and achieves 54 percent ~ 91 percent power efficiency. It is designed to work with a constant switching frequency of 3MHz. Without sacrificing output frequency spectrum or output ripple, an efficiency improvement of up to 20 percent is obtained at light load.

Power consumption is the primary concern in battery-operated portable applications. Buck converters have gained popularity in powering portable devices due to their compact size, good current delivery capability and high efficiency. However, portable devices are operating under light load condition for the most of the time. Conventional buck converters suffer from low light-load efficiency which severely limits battery lifetime. In this project, a novel technique for buck converter is proposed to reduce the switching loss by reducing the effective input supply voltage at light load. This is achieved by switching between two different input voltages (3.3V and 1.65V) depending on the output current value. Experimental results show that this technique improves the efficiency at light loads by 18.07%. The buck voltage possesses an output voltage of 0.9V and provides a maximum output current of 400mA. The buck converter operates at a switching frequency of 1MHz. The prototype was fabricated using 0.18µm CMOS technology, and occupies a total active area of 0.6039mm^2.