Power consumption and device size have been placed at the primary concerns for battery-operated portable applications. Switching converters gain popularity in powering portable devices due to their high efficiency, compact sizes and high current delivery capability. However portable devices usually operate at light loads most of the time and are only required to deliver high current in very short periods, while conventional buck converter suffers from low efficiency at light load due to the switching losses that do not scale with load current. In this research, a novel technique for buck converter is proposed to reduce the switching loss by reducing the effective voltage supply at light load. This buck converter, implemented in TSMC 0.18 micrometers CMOS technology, operates with a input voltage of 3.3V and generates an output voltage of 0.9V, delivers a load current from 1mA to 400mA, and achieves 54 percent ~ 91 percent power efficiency. It is designed to work with a constant switching frequency of 3MHz. Without sacrificing output frequency spectrum or output ripple, an efficiency improvement of up to 20 percent is obtained at light load.

Power consumption is the primary concern in battery-operated portable applications. Buck converters have gained popularity in powering portable devices due to their compact size, good current delivery capability and high efficiency. However, portable devices are operating under light load condition for the most of the time. Conventional buck converters suffer from low light-load efficiency which severely limits battery lifetime. In this project, a novel technique for buck converter is proposed to reduce the switching loss by reducing the effective input supply voltage at light load. This is achieved by switching between two different input voltages (3.3V and 1.65V) depending on the output current value. Experimental results show that this technique improves the efficiency at light loads by 18.07%. The buck voltage possesses an output voltage of 0.9V and provides a maximum output current of 400mA. The buck converter operates at a switching frequency of 1MHz. The prototype was fabricated using 0.18µm CMOS technology, and occupies a total active area of 0.6039mm^2.

Power consumption of smart cameras varies significantly between sleep mode and active mode, and a smart camera operates in sleep mode for 80 — 90% of time for typical use. To prolong the battery life of smart cameras, it is essential to increase the power converter efficiency for light load, while being able to manage heavy load. The power stage of traditional buck converter is optimized for maximum load, at the cost of light-load efficiency. Wei proposed a multiphase buck converter incorporating the baby-buck concept and optimum number of phases (ONP) control. This thesis research investigated Wei's multiphase buck converter to improve the light-load efficiency for smart cameras as the target application. The proposed two-phase buck converter aims to provide power for microprocessors of smart cameras. The input voltage of the converter is 5 V DC, and the output voltage is 1.2 V DC with power dissipation range of 25 mA (30 mW) for light load and 833 mA (1 W) for heavy load. Three methods are considered to improve light-load efficiency: adopting baby-buck concept, adapting ONP control for low-power range, and implementing a pulse frequency modulation (PFM) control scheme with discontinuous conduction mode (DCM) to lower switching frequency. The first method is to adopt the baby-buck concept through power stage design of each phase to optimize efficiency for a specific load range. The baby-buck phase is optimized for light load and the heavy-load phase is designed to handle the processors maximum power consumption. The second method performs phase selection from sensed load current information. Rather than have all phases active for heavy-load as in ONP control, optimum phase selection (OPS) control is introduced to adaptively select between phases based on load current. Due to low-power constraints, OPS is more efficient for the medium to heavy-load range. The transition between phases due to load change is also investigated. The third and final method implements PFM control with DCM to lower switching frequency and reduce switching and driving losses under light load. PFM is accomplished with a constant on-time (COT) valley current mode controller, which uses the inductor current information and output voltage to generate switching signals for both the top and bottom switches. The baby-buck phase enters DCM to lower switching frequency under very light load, while the heavy-load phase remains in continuous conduction mode (CCM) throughout its load range. The proposed two-phase buck converter is designed and prototyped using discrete components. Efficiency of the two-phase converter and a power loss breakdown for each block in the control scheme were measured. The efficiency ranges from 64% to 81% for light load ranging of 30 mW to 200 mW, and the efficiency ranges from 81% to 88% for heavy load ranging from 200 mW to 1 W. The majority loss is due to controllers, which are responsible for 37 % (8.6 mW) for light load of 60 mW and for 10.9 % (9 mW) for heavy load of 600 mW. The gate driver loss is considerable for heavy load of 600 mW, consuming 11.9% (9.8mW). The converter has a 10 mV overshoot voltage for a load step-down from 225 mA to 25 mA, and it has 65 mV overshoot voltage for a load step-up from 25 mA to 225 mA. Although, a fair comparison is difficult due to use of discrete parts for OPS control, the proposed converter shows reasonably good efficiency and performance. / Master of Science

In order to extend the battery life of smart cameras, it is essential to increase the efficiency of power converters, especially at light load. This thesis research investigated a power converter to supply power for the microprocessor of a smart camera. The input voltage of the converter is 5 V, and the output voltage is 1.2 V with the load ranging from 10 mA (12 mW) to 1200 mA (1440 mW). The conventional buck converter is typically optimized for high efficiency at maximum load at the cost of light-load efficiency. A converter is investigated in this thesis to improve light load efficiency, while being able to handle heavy load, to prolong the battery life of smart cameras. The proposed converter employs two modes, a baby-buck mode and a heavy-load mode, in which each mode is optimized for its respective load range to achieve high efficiency throughout entire range. The heavy-load mode converter adopts the conventional synchronous buck approach, as it generally achieves high efficiency at heavy load. However, the synchronous buck approach is inefficient at light load due to the large switching, driving, and controller losses. The proposed baby-buck mode converter employs the following schemes or technique to reduce those losses. First, the baby buck mode converter adopts pulse frequency modulation (PFM) with discontinuous conduction mode (DCM) to lower the switching frequency at light load, so frequency-dependent switching and driving losses are reduced. Second, a simple control scheme, constant on-time V2 control, is adopted to simplify the controller and hence minimize the controller power dissipation. Third, the top switch of the baby-buck mode uses a small MOSFET, which is optimized for light load, and the bottom switch uses Schottky diode in lieu of a MOSFET to simplify the COT V2 controller. Fourth, the proposed converter combines the heavy-load and baby-buck mode converter into a single converter with a shared inductor, capacitors, and the feedback controller to save space. Finally, a simple and low power feedback controller with an optimum mode selector, a COT V 2 controller, and gate drivers are designed. The optimum mode selector selects an appropriate mode based on the load condition, while shutting down the opposing mode. The proposed converter was fabricated in CMOS 0.25 µm technology in two phases. Phase 1 contains design of the proposed converter with open loop, and its functionality is verified through measurements of test chips. Phase 2 includes the entire converter design with the feedback controller. Since the test chips of phase 2 are not delivered, yet, its functionality during the steady state and transient responses are verified through simulations. Simulation results indicate that the efficiency of the proposed converter ranges from 74% to 93% at 12 mW and 1440 mW, respectively. This result demonstrates that the proposed converter can achieve higher efficiency for the entire load range when compared to an off-the-shelf synchronous buck converters. / Master of Science

As information technology advances, so does the demand for power management of telecom and computing equipment. High efficiency and high power density are still the key technology drivers for power management for these applications. In order to save energy, in 2005, the U.S. Environmental Protection Agency (EPA) announced the first draft of its proposed revision to its ENERGY STAR specification for computers. The draft specification separately addresses efficiency requirements for laptop, desktop, workstation and server computers. The draft specification also proposes a minimum power supply efficiency of 80% for PCs and 75% to 83% for desktop derived servers, depending on loading condition and server type. Furthermore, recently some industry companies came out with a much higher efficiency target for the whole AC/DC front-end converter over a wide load range. Distributed power systems are widely adopted in the telecom and computing applications for the reason of high performance and high reliability. As one of the key building blocks in distributed power systems, DC/DC converters in the front-end converter are also under the pressure of increasing efficiency and power density. Due to the hold-up time requirement, PWM DC/DC converters cannot achieve high efficiency for well known reasons when they are designed for wide input voltage range. As a promising topology for this application, LLC resonant converters can achieve both high efficiency and wide input voltage range capability because of its voltage gain characteristics and small switching loss. However, the efficiency of LLC resonant converter with diode rectifier still cannot meet the recent efficiency target from industry. In order to further improve efficiency of LLC resonant converters, synchronous rectification must be used. The complete solution of synchronous rectification of LLC resonant converters is discussed in this thesis. The driving of the synchronous rectifier can be realized by sensing the voltage Vds of the SR. The turn-on of the SR can be triggered by the body-diode conduction of the SR. With the Vds compensation network, the precise voltage drop on Rds_on can be achieved, thus the SR can be turned off at the right time. Moreover, efficiency optimization at normal operation over wide load range is discussed. It is revealed that power loss at normal operation is solely determined by the magnetizing inductance while the magnetizing inductor is designed according to dead-time td selection. The mathematic equations for the relationship between power loss and dead-time are developed. For the first time, the relationship between power loss and dead-time is used as a tool for efficiency optimization. With this tool, the efficiency optimization of the LLC resonant converter can be made according to efficiency requirement over a wide load range. With the expectation to achieve high efficiency at ultra-light load, the green mode operation of LLC resonant converters is addressed. The rationale of the issue with the conventional control algorithm is revealed and a preliminary solution is proposed. / Master of Science

Smart cameras operate mostly in sleep mode, which is light load for power supplies. Typical buck converter applications have low efficiency under the light load condition, primarily from their power stage and control being optimized for heavy load. The battery life of a smart camera can be extended through improvement of the light load efficiency of the buck converter. This thesis research investigated the first stage converter of a car black box to provide power to a microprocessor, camera, and several other peripherals. The input voltage of the converter is 12 V, and the output voltage is 5 V with the load range being 20 mA (100 mW) to 1000 mA (5000 mW). The primary design objective of the converter is to improve light load efficiency. A 3-level buck converter and its control scheme proposed by Reusch were adopted for the converter in this thesis. A 3-level buck converter has two more MOSFETs and one more capacitor than a synchronous buck converter. Q1 and Q2 are considered the top MOSFETs, while Q3 and Q4 are the synchronous ones. The extra capacitor is used as a second power source to supply the load, which is connected between the source of Q1 and the drain of Q2 and the source of Q3 and the drain of Q4. The methods considered to improve light load efficiency are: PFM (pulse frequency modulation) control scheme with DCM (discontinuous conduction mode) and use of Schottky diodes in lieu of the synchronous MOSFETs, Q3 and Q4. The 3-level buck converter operates in CCM for heavy load above 330 mA and DCM for light load below 330 mA. The first method uses a COT (constant on-time) valley current mode controller that has a built in inductor current zero-crossing detector. COT is used to implement PFM, while the zero-crossing detector allows for DCM. The increase in efficiency comes from reducing the switching frequency as the load decreases by minimizing switching and gate driving loss. The second method uses an external current sense amplifier and a comparator to detect when to shut down the gate drivers for Q3 and Q4. Schottky diodes in parallel with Q3 and Q4 carry the load current when the MOSFETs are off. This increases the efficiency through a reduction in switching loss, gate driving loss, and gate driver power consumption. The proposed converter is prototyped using discrete components. LTC3833 is used as the COT valley current mode controller, which is the center of the control scheme. The efficiency of the 3-level buck converter was measured and ranges from 82% to 95% at 100 mW and 5000 mW, respectively. The transient response of the converter shows no overshoot due to a 500 mA load step up or down, and the output voltage ripple is 30 mV. The majority of the loss comes from the external components, which include a D FF (D flip-flop), AND gate, OR gate, current sense chip, comparator, and four gate drivers. The proposed converter was compared to two off-the-shelf synchronous buck converters. The proposed converter has good efficiency and performance when compared to the other converters, despite the fact that the converter is realized using discrete components. / Master of Science

The proliferation of electronic equipment that is permanently connected to the grid causes significant parasitic losses. Yet, the design of power supplies for PCs, servers, multi-function printers, etc, is governed by the cost and component specifications at the peak operating point as well as the thermal management of the power supply itself. Most power supplies have lower efficiencies at light loads than at their rated loads. If the unit spends most of its time at the light load operating point, then the energy consumption will be much higher compared to a situation where the power supply is optimized for overall energy consumption with a specified load cycle. Considering that most electronic appliances are produced in high volume, the use of power supplies that permit easy custom design makes sense from the standpoint of energy efficiency. Over the past few years, multiple topological changes and design changes that aim to improve the efficiency of the power supplies have been proposed. However, their proliferation in low cost consumer electronics has been limited primarily by their high costs, additional area overhead and incompatibility with existing power supply converter topologies. As a part of this Master's thesis research work, a business case is first proposed to show that a market for low cost and high power rating electronic devices that exhibits high power efficiency exists. Then a novel yet simple, low cost device(SSSR) is proposed to improve the efficiency of existing power supplies without effecting major changes to their existing design. Our claims are backed up by simulation results and a working prototype. Finally, a ROI model is presented to showcase the effectiveness of the proposed solution in today's consumer market.

The world is heading towards an energy crisis and desperate efforts are being made to find an alternative, reliable and clean source of energy. Solar Energy is one of the most clean and reliable source of renewable energy on earth. Conventionally, extraction of solar power for electricity generation was limited to PV farms, however lately Distributed Generation form of Solar Power has emerged in the form of residential and commercial Grid Tied Micro-Inverters. Grid Tied Micro-Inverters are costly when compared to their string type counterparts because one inverter module is required for every single or every two PV panels whereas a string type micro-inverter utilizes a single inverter module over a string of PV panels. Since in micro-inverter every panel has a dedicated inverter module, more power per panel can be extracted by performing optimal maximum power tracking over single panel rather than over an entire string of panels. Power per panel extracted by string inverters may be lower than its maximum value as few of the panels in the string may or may not be shaded and thereby forming the weaker links of the system. In order to justify the higher costs of Micro-Inverters, it is of utmost importance to convert the available power with maximum possible efficiency. Typically, a microinverter consists of two important blocks; a Front End DC-DC Converter and Output DCAC Inverter. This thesis proposes efficiency optimization techniques for both the blocks of the micro-inverter. iv Efficiency Optimization of Front End DC-DC Converter This thesis aims to optimize the efficiency of the front end stage by proposing optimal design procedure for resonant parameters of LLC Topology as a Front End DC-DC Converter for PV Applications. It exploits the I-V characteristics of a solar panel to design the resonant parameters such that resonant LLC topology operates near its resonant frequency operating point which is the highest efficiency operating point of LLC Converter. Efficiency Optimization of Output DC-AC Inverter Due to continuously variable irradiance levels of solar energy, available power for extraction is constantly varying which causes the PV Inverter operates at its peak load capacity for less than 15% of the day time. Every typical power converter suffers through poor light load efficiency performance because of the load independent losses present in a power converter. In order to improve the light load efficiency performance of Three Phase Inverters, this thesis proposes Phase Skipping Control technique for Three Phase Grid Tied Micro-Inverters. The proposed technique is a generic control technique and can be applied to any inverter topology, however, in order to establish the proof of concept this control technique has been implemented on Three Phase Half Bridge PWM Inverter and its analysis is provided. Improving light load efficiency helps to improve the CEC efficiency of the inverter.