La tendance actuelle dans le domaine des télécommunications mène à des systèmes capables de fonctionner selon plusieurs standards, et donc plusieurs fréquences porteuses. La synthèse de la fréquence porteuse est un élément clef, dont les propriétés reposent essentiellement sur les performances de l’oscillateur employé. Pour assurer le fonctionnement de systèmes compatibles avec plusieurs standards de télécommunication, la solution conventionnelle consiste à intégrer plusieurs oscillateurs locaux. Cette solution est coûteuse, d’autant plus que, malgré le fait que les technologies actuelles atteignent des niveaux d’intégration très importants, la surface occupée par des oscillateurs traditionnels de type LC ne peut pas être diminuée, alors que le coût de fabrication au millimètre carré devient de plus en plus élevé. Il serait donc très intéressant de remplacer les oscillateurs LC, ce qui nous amène à rechercher des solutions alternatives parmi de nouvelles technologies. L’oscillateur spintronique (STO) est un nouveau dispositif issu des études sur les couches minces magnétiques. Il apparait comme un candidat potentiel de remplacement des oscillateurs LC du fait de sa grande accordabilité en fréquence et de son faible encombrement. Toutefois des mesures effectuées sur les STOs ont montré que la performance en puissance et en bruit de phase d’un oscillateur seul ne permet pas de remplir les spécifications pour des applications de télécommunication. Nous proposons de remplir ces spécifications en couplant un nombre d’oscillateurs spintroniques important. Dans ce cadre se posent plusieurs questions qui concernent les procédures de modélisation, d’analyse et de synthèse des systèmes interconnectés. Les procédures de modélisation incluent la démarche de recherche de modèles à complexité croissante qui décrivent les propriétés entrée-sortie d’un oscillateur spintronique, ainsi que la démarche de généralisation des modèles des oscillateurs dans le cadre du réseau. Les procédures d’analyse cherchent à vérifier la stabilité et évaluer la performance des systèmes interconnectés. Les procédures de synthèse permettent de concevoir des interconnexions sophistiquées pour les oscillateurs afin d’assurer toutes les spécifications du cahier des charges. Dans ce document, nous établissons tout d’abord le problème de la synthèse de fréquence par couplage avec un cahier des charges formalisé en termes de gabarits fréquentiels sur des densités spectrales de puissance. Le cahier des charges posé amène la nécessité de modéliser l’oscillateur spintronique pour pouvoir simuler et analyser son comportement. Ici, nous proposons une modélisation originale selon des degrés de complexité croissante. Ensuite, nous discutons de la structure de la commande de l’ensemble des oscillateurs afin de remplir les spécifications du cahier des charges. La structure de commande proposée nécessite de développer une méthode de conception des interconnexions du réseau d’après les critères de performance. Dans les deux derniers chapitres, nous proposons deux méthodes fréquentielles de synthèse originales pour résoudre le problème de synthèse de fréquence par couplage. La première méthode de synthèse permet de prendre en compte un critère mathématique du cahier des charges, qui correspond à un gabarit fréquentiel à respecter, et permet d’obtenir une matrice d’interconnexion des sous-systèmes, telle que le module de la réponse fréquentielle du réseau approxime le gabarit imposé par le cahier des charges. La deuxième méthode de synthèse permet de prendre en compte plusieurs gabarits fréquentiels à la fois. La solution obtenue est une matrice d’interconnexion des sous-systèmes, qui résout le problème de la synthèse de fréquence par couplage d’oscillateurs spintroniques. / The current trends in telecommunication are leading to systems that are compatible with multiple standards and consequently multiple carrier frequencies. The frequency synthesis is a key element influenced by the local oscillator performance. In order to ensure the system compatibility with multiple telecommunication standards, the conventional solution consists in using one local oscillator for each standard. This solution is expensive, even more, since the cost per squared millimetre is increasing, while the silicon area occupied by the traditional LC-tank oscillators cannot be reduced in spite of the fact that technology is going to higher integration levels. Thus, it should be interesting to find a substitution to the LC-tank oscillators which leads to research for alternative solutions among new technologies. The spin torque oscillator (STO) is a new device issued from the ferromagnetic thin-film research. Due to its frequency accord ability and its capability to occupy relatively small volume, it appears as a potential candidate for the LC-tank oscillator replacement. However, a set of measurements prove that these devices exhibit poor power and phase noise performance, making them unable to fulfill the technical specification of the radiofrequency applications. We propose to reach these specifications by coupling of a large number of spin torque oscillators. In this scope, numerous questions appear regarding the procedures of modelling, analysis and synthesis of the complex interconnected systems. The modelling procedures are dedicated to the increasing complexity models that describe the input-output behaviour of a spin torque oscillator and its behaviour within the interconnected network. The analysis procedures are targeted to verify the stability and to evaluate the performance level of the interconnected systems. The synthesis procedures allow to design the interconnection law for spin torque oscillators in order to fulfill the technical requirements. In this document, the frequency synthesis problem by spin torque oscillator coupling with technical specification description in terms of power spectral densities is established. The formulated specifications introduce the problem of the oscillator modelling in order to perform a simulation and an analysis of the oscillator behaviour. Here, we propose an original model using several conventional models with increasing complexity. An original oscillator network model that describes qualitative properties of the oscillator synchronisation is introduced. Afterwards, the control law architecture for an oscillator set is established in order to accomplish the technical requirement specifications. The suggested control architecture needs to be developed with quantitative systematic and efficient design method for the network interconnection taking into account the formulated performance criteria. In the last two chapters we propose two original frequency domain design methods allowing the resolution of our frequency synthesis problem. The first design method allows to consider explicitly a performance criterium corresponding toa desired frequency constraint. The method allows to obtain a suitable sub-system interconnection matrix that fits the frequency specification constraint. The second design method allows to find an interconnection matrix and to take into account simultaneously several frequency specification constraints. The interconnection matrix obtained with the proposed method solves the problem of frequency synthesis by coupling of spin torque oscillators.

Network on Chips[1][2][3][4] are critical elements of modern System on Chip(SoC) as well as Chip Multiprocessor(CMP)designs. Network on Chips (NoCs) help manage high complexity of designing large chips by decoupling computation from communication. SoCs and CMPs have a multiplicity of communicating entities like programmable processing elements, hardware acceleration engines, memory blocks as well as off-chip interfaces. With power having become a serious design constraint[5], there is a great need for designing NoC which meets the target communication requirements, while minimizing power using all the tricks available at the architecture, microarchitecture and circuit levels of the de-sign. This thesis presents a holistic, QoS based, power optimal design solution of a NoC inside a CMP taking into account link microarchitecture and processor tile configurations. Guaranteeing QoS by NoCs involves guaranteeing bandwidth and throughput for connections and deterministic latencies in communication paths. Label Switching based Network-on-Chip(LS-NoC) uses a centralized LS-NoC Management framework that engineers traffic into QoS guaranteed routes. LS-NoC uses label switching, enables band-width reservation, allows physical link sharing and leverages advantages of both packet and circuit switching techniques. A flow identification algorithm takes into account band-width available in individual links to establish QoS guaranteed routes. LS-NoC caters to the requirements of streaming applications where communication channels are fixed over the lifetime of the application. The proposed NoC framework inherently supports heterogeneous and ad-hoc SoC designs. A multicast, broadcast capable label switched router for the LS-NoC has been de-signed, verified, synthesized, placed and routed and timing analyzed. A 5 port, 256 bit data bus, 4 bit label router occupies 0.431 mm2 in 130nm and delivers peak band-width of80Gbits/s per link at312.5MHz. LS Router is estimated to consume 43.08 mW. Bandwidth and latency guarantees of LS-NoC have been demonstrated on streaming applications like Hiper LAN/2 and Object Recognition Processor, Constant Bit Rate traffic patterns and video decoder traffic representing Variable Bit Rate traffic. LS-NoC was found to have a competitive figure of merit with state-of-the-art NoCs providing QoS. We envision the use of LS-NoC in general purpose CMPs where applications demand deterministic latencies and hard bandwidth requirements. Design variables for interconnect exploration include wire width, wire spacing, repeater size and spacing, degree of pipelining, supply, threshold voltage, activity and coupling factors. An optimal link configuration in terms of number of pipeline stages for a given length of link and desired operating frequency is arrived at. Optimal configurations of all links in the NoC are identified and a power-performance optimal NoC is presented. We presents a latency, power and performance trade-off study of NoCs using link microarchitecture exploration. The design and implementation of a framework for such a design space exploration study is also presented. We present the trade-off study on NoCs by varying microarchitectural(e.g. pipelining) and circuit level(e.g. frequency and voltage) parameters. A System-C based NoC exploration framework is used to explore impacts of various architectural and microarchitectural level parameters of NoC elements on power and performance of the NoC. The framework enables the designer to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. Latency, power and throughput results using this framework to study a 4x4 CMP are presented. The framework is used to study NoC designs of a CMP using different classes of parallel computing benchmarks[6]. One of the key findings is that the average latency of a link can be reduced by increasing pipeline depth to a certain extent, as it enables link operation at higher link frequencies. Abstract There exists an optimum degree of pipelining which minimizes the energy-delay product of the link. In a 2D Torus when the longest link is pipelined by 4 stages at which point least latency(1.56 times minimum) is achieved and power(40% of max) and throughput (64%of max) are nominal. Using frequency scaling experiments, power variations of up to40%,26.6% and24% can be seen in 2D Torus, Reduced 2D Torus and Tree based NoC between various pipeline configurations to achieve same frequency at constant voltages. Also in some cases, we find that switching to a higher pipelining configuration can actually help reduce power as the links can be designed with smaller repeaters. We also find that the overall performance of the ICNs is determined by the lengths of the links needed to support the communication patterns. Thus the mesh seems to perform the best amongst the three topologies(Mesh, Torus and Folded Torus) considered in case studies. The effects of communication overheads on performance, power and energy of a multiprocessor chip using L1,L2 cache sizes as primary exploration parameters using accurate interconnect, processor, on-chip and off-chip memory modelling are presented. On-chip and off-chip communication times have significant impact on execution time and the energy efficiency of CMPs. Large cache simply larger tile area that result in longer inter-tile communication link lengths and latencies, thus adversely impacting communication time. Smaller caches potentially have higher number of misses and frequent of off-tile communication. Energy efficient tile design is a configuration exploration and trade-off study using different cache sizes and tile areas to identify a power-performance optimal configuration for the CMP. Trade-offs are explored using a detailed, cycle accurate, multicore simulation frame-work which includes superscalar processor cores, cache coherent memory hierarchies, on-chip point-to-point communication networks and detailed interconnect model including pipelining and latency. Sapphire, a detailed multiprocessor execution environment integrating SESC, Ruby and DRAM Sim was used to run applications from the Splash2 benchmark(64KpointFFT).Link latencies are estimated for a16 core CMP simulation on Sapphire. Each tile has a single processor, L1 and L2 caches and a router. Different sizesofL1 andL2lead to different tile clock speeds, tile miss rates and tile area and hence interconnect latency. Simulations across various L1, L2 sizes indicate that the tile configuration that maximizes energy efficiency is related to minimizing communication time. Experiments also indicate different optimal tile configurations for performance, energy and energy efficiency. Clustered interconnection network, communication aware cache bank mapping and thread mapping to physical cores are also explored as potential energy saving solutions. Results indicate that ignoring link latencies can lead to large errors in estimates of program completion times, of up to 17%. Performance optimal configurations are achieved at lower L1 caches and at moderateL2 cache sizes due to higher operating frequencies and smaller link lengths and comparatively lesser communication. Using minimal L1 cache size to operate at the highest frequency may not always be the performance-power optimal choice. Larger L1 sizes, despite a drop in frequency, offer a energy advantage due to lesser communication due to misses. Clustered tile placement experiments for FFT show considerable performance per watt improvement (1.2%). Remapping most accessed L2 banks by a process in the same core or neighbouring cores after communication traffic analysis offers power and performance advantages. Remapped processes and banks in clustered tile placement show a performance per watt improvement of5.25% and energy reductionof2.53%. This suggests that processors could execute a program in multiple modes, for example, minimum energy, maximum performance.

This diploma thesis deals with the study of the new development of the current development area of the town of Kroměříž in its northeastern part behind the psychiatric hospital between the streets Lutopecká and Havlíčková. This territory connects the local part of Terezov and Barbořina. The aim of the study was to propose new housing for more than 1,200 inhabitants in a currently unbuilt area in accordance with a valid territorial plan. The solved territory is divided into three stages of construction. The northeastern part follows the existing housing development with two-storey apartment buildings. In the rest of the area there are designed individual houses and partly terraced houses. The area is complemented by a kindergarten, shops and a parking house. In accordance with the territorial plan there is also a park and a sports ground with a playground and a sports hall. The character of the territory is greatly influenced by some already existing engineering networks and their protection zones, the transfer of which is economically disadvantageous. Due to the marginal position of the solved territory, the study proposes the extension of the service by public transportation by another two places. The new transport link between streets Lutopecká and Havlíčková would cause a significant traffic movement to increase over the area, so the study envisages a calm traffic in the form of a maximum speed limitation of 30 km/h and the communication system consists of two-way and one-way communications. Transportation is provided by the garages belonging to family houses supported with parking along the roads. In the apartment part, parking is possible in the outdoor parking lots and to supplement the necessary capacity, the study also proposes a parking house.

The urban study deals with the design of the new city district in the area where the Tepna Náchod textile factory used to stand. The total area of the solved area (including the existing development) is 10.35 ha. My intention was to create a new neighborhood that will take advantage of the huge benefits of this area. These are the terrain configuration and the immediate proximity of the historic city center and the train and bus stations. Because the area is flat and it is one of the few in the city that is not on the slope, I decided to place a compact block of flats and make the most of the area. The aim was to design a new city district, basically a modern city center, but it will not compete with the historic one, but rather will support it. The newly designed public spaces are not critical in their size, but in their content and diversity. The main idea of the proposal was to use the proximity of the railway station, the historic center and the terrain and create a barrier-free city district for the inhabitants, which will connect the surrounding city districts and at the same time offer enough housing, places for business and also a leisure time environment. And everything is within walking distance of the station and the center.

The main goal of this master’s thesis is to represent the development of accounting softwares depending on the development of electronic banking. Particular chapters subsequently deal with direct banking - its formation, services and security, concerning accounting software as well as the interconnection of banks and the company accountancy using conversion applications integrated into the economical software.

This thesis provides an analysis of the application for evolutionary scheduling of collective communications. It proposes possible ways to accelerate the application using general purpose computing on graphics processing units (GPU). This work offers a theoretical overview of systems on a chip, collective communications scheduling and more detailed description of evolutionary algorithms. Further, the work provides a description of the GPU architecture and its memory hierarchy using the OpenCL memory model. Based on the profiling, the work defines a concept for parallel execution of the fitness function. Furthermore, an estimation of the possible level of acceleration is presented. The process of implementation is described with a closer insight into the optimization process. Another important point consists in comparison of the original CPU-based solution and the massively parallel GPU version. As the final point, the thesis proposes distribution of the computation among different devices supported by OpenCL standard. In the conclusion are discussed further advantages, constraints and possibilities of acceleration using distribution on heterogenous computing systems.

The aim of the thesis is to design a steel structure of the parking building in the center of Brno. The plan dimensions of the building are 29 x 77.5 m including a missing corner of the dimensions 5 x 12.5 m in the southeast part of the construction. The construction of the parking building has 4 above-ground floors with the same layout and the fifth floor situated only in the middle section of the construction. Each floor is 3.5 m high. The total height of the construction in the place of the roofed part of the fifth floor is 17.5 m, otherwise 14 m. A spatial frame is the main load-bearing part consisting of 7 fields in the longitudinal direction and 5 fields in the transversal direction. The spatial frame is formed of columns and longitudinal and transversal girders. Steel-concrete composite joists are pin-supported among longitudinal girders. The construction of the parking building is solved in three versions considering different placing of columns to the base structure and different placing of longitudinal and transversal girders to the columns. The resulting draft is worked out in details. Roof cladding will be made using sandwich panels and walls will be made out of glass panels. The calculation has been done in Scia Engineer 2014 program and by manual calculation.

Beaucoup de services vitaux de la vie quotidienne dépendent de systèmes d'ingénierie hautement complexes et interconnectés; Ces systèmes sont constitués d'un grand nombre de capteurs interconnectés, d'actionneurs et de composants du système. L'étude des systèmes interconnectés joue un rôle important dans l'étude de la fiabilité des systèmes dynamiques; car elle permet d'étudier les propriétés d'un système interconnecté en analysant ses sous-composants moins complexes. Le diagnostic des pannes est essentiel pour assurer des opérations sûres et fiables des systèmes de contrôle interconnectés. Dans toutes les situations, le système global et / ou chaque sous-système peuvent être analysés à différents niveaux pour déterminer la fiabilité du système global. Dans certains cas, il est important de déterminer les informations anormales des variables internes du sous-système local, car ce sont les causes qui contribuent au fonctionnement anormal du processus global. Cette thèse porte sur les défis de l'application de la théorie inverse du système et des techniques FDD basées sur des modèles pour traiter le problème articulaire du diagnostic des fautes et de l'analyse des causes racines (FD et RCA). Nous étudions ensuite le problème de l'inversibilité de la gauche, de l'observabilité et de la diagnosticabilité des fauts du système interconnecté, formant un algorithme FD et RCA multi-niveaux basé sur un modèle. Ce système de diagnostic permet aux composants individuels de surveiller la dynamique interne localement afin d'améliorer l'efficacité du système et de diagnostiquer des ressources de fautes potentielles pour localiser un dysfonctionnement lorsque les performances du système global se dégradent. Par conséquent, un moyen d'une combinaison d'intelligence locale avec une capacité de diagnostic plus avancée pour effectuer des fonctions FDD à différents niveaux du système est fourni. En conséquence, on peut s'attendre à une amélioration de la localisation des fauts et à de meilleurs moyens de maintenance prédictive. La nouvelle structure du système, ainsi que l'algorithme de diagnostic des fautes, met l'accent sur l'importance de la RCA de défaut des dispositifs de terrain, ainsi que sur l'influence de la dynamique interne locale sur la dynamique globale. Les contributions de cette thèse sont les suivantes: Tout d'abord, nous proposons une structure de système non linéaire interconnecté inversible qui garantit le fauts dans le sous-système de périphérique de terrain affecte la sortie mesurée du système global de manière unique et distincte. Une condition nécessaire et suffisante est développée pour assurer l'inversibilité du système interconnecté qui nécessite l'inversibilité de sous-systèmes individuels. Deuxièmement, un observateur interconnecté à deux niveaux est développé; Il se compose de deux estimateurs d'état, vise à fournir des estimations précises des états de chaque sous-système, ainsi que l'interconnexion inconnue. En outre, il fournira également une condition initiale pour le reconstructeur de données et le filtre de fauts local une fois que la procédure FD et RCA est déclenchée par tout fauts. D'une part, la mesure utilisée dans l'estimateur de l'ancien sous-système est supposée non accessible; La solution est de la remplacer par l'estimation fournie par l'estimateur de ce dernier sous-système. / Many of the vital services of everyday life depend on highly complex and interconnected engineering systems; these systems consist of large number of interconnected sensors, actuators and system components. The study of interconnected systems plays a significant role in the study of reliability theory of dynamic systems, as it allows one to investigate the properties of an interconnected system by analyzing its less complicated subcomponents. Fault diagnosis is crucial in achieving safe and reliable operations of interconnected control systems. In all situations, the global system and/or each subsystem can be analyzed at different levels in investigating the reliability of the overall system; where different levels mean from system level down to the subcomponent level. In some cases, it is important to determine the abnormal information of the internal variables of local subsystem, in order to isolate the causes that contribute to the anomalous operation of the overall process. For example, if a certain fault appears in an actuator, the origin of that malfunction can have different causes: zero deviation, leakage, clogging etc. These origins can be represented as root cause of an actuator fault. This thesis concerns with the challenges of applying system inverse theory and model based FDD techniques to handle the joint problem of fault diagnosis & root cause analysis (FD & RCA) locally and performance monitoring globally. By considering actuator as individual dynamic subsystem connected with process dynamic subsystem in cascade, we propose an interconnected nonlinear system structure. We then investigate the problem of left invertibility, fault observability and fault diagnosability of the interconnected system, forming a novel model based multilevel FD & RCA algorithm. This diagnostic algorithm enables individual component to monitor internal dynamics locally to improve plant efficiency and diagnose potential fault resources to locate malfunction when operation performance of global system degrades. Hence, a means of acombination of local intelligence with a more advanceddiagnostic capability (combining fault monitoring anddiagnosis at both local and global levels) to performFDDfunctions on different levels of the plantis provided. As a result, improved fault localization and better predictive maintenance aids can be expected. The new system structure, together with the fault diagnosis algorithm, is the first to emphasize the importance of fault RCA of field devices, as well as the influences of local internal dynamics on the global dynamics. The developed model based multi-level FD & RCA algorithm is then a first effort to combine the strength of the system level model based fault diagnosis with the component level model based fault diagnosis. The contributions of this thesis include the following: Firstly, we propose a left invertible interconnected nonlinear system structure which guarantees that fault occurred in field device subsystem will affect the measured output of the global system uniquely and distinguishably. A necessary and sufficient condition is developed to ensure invertibility of the interconnected system which requires invertibility of individual subsystems. Second, a two level interconnected observer is developed which consists of two state estimators, aims at providing accurately estimates of states of each subsystem, as well as the unknown interconnection. In addition, it will also provide initial condition for the input reconstructor and local fault filter once FD & RCA procedure is triggered by any fault. Two underlyingissues are worth to be highlighted: for one hand, the measurement used in the estimator of the former subsystem is assumed not accessible; the solution is to replace it by the estimate provided by the estimator of the latter subsystem. In fact, this unknown output is the unknown interconnection of the interconnected system, and also the input of the latter subsystem.

This MSc Thesis is focused on the multimodeling area, especially on the cooperation of the C++ language and the Prolog language. The recent research is established on my semester study, which also dealt with the multimodeling area. During this research a prototype of interconnection library for cooperation of above mentioned programming languages was developed. This prototype of the library was finished within the scope of this thesis and some case-studies were created, too, using also another simulation library - SIMLIB/C++. These case-studies have their focus in the problems of artificial intelligence. The main benefit of this thesis is the confrontation of methods with and without using artificial intelligence.

Die Arbeit beschreibt verschiedene technische Ansätze zur Bestimmung der Alterung der Chip-Substrat-Verbindung. Eine der Schlüsseltechnologien ist hierbei die Bestimmung der virtuellen Sperrschichttemperatur. Es werden in der Arbeit verschiedene Möglichkeiten zur Bestimmung der virtuellen Chiptemperatur von IGBTs und der Alterung der Chip-Substrat-Verbindung vorgestellt und mit ihren Vor- und Nachteilen in der Umsetzbarkeit und in der Anwendbarkeit im Umrichter diskutiert. Besondere Betrachtung findet dabei unter anderem die technische Umsetzung einer Messmethode, die auf einer kurzzeitigen Belastung im aktiven Bereich mit anschließender Bestimmung des Abkühlverhaltens basiert. Über einen Vergleich mit dem ursprünglichen Abkühlverhalten ist es mit den vorgestellten Verfahren gut möglich, die Chipalterung zu detektieren. Weiterhin wird ein Verfahren vorgestellt, das die Bestimmung der virtuellen Chiptemperatur im Umrichter über eine Ermittlung der Millerplateauhöhe im Abschaltmoment des IGBTs ermöglicht.:1 Einleitung 2 Alterung von Leistungshalbleitern 3 Stand der Technik der Chiptemperaturbestimmung in der Umrichterschaltung 4 Untersuchungen temperaturabhängiger elektrischer Bauelementparameter 5 Wichtige Verfahren zur Bestimmung der Chiptemperatur in der Umrichterschaltung 6 Untersuchung eines Verfahrens zur Bestimmung der Chiptemperatur in der Umrichterschaltung mittels Millerplateauhöhe 7 Technische Umsetzbarkeit der gezeigten Messverfahren 8 Zusammenfassung und Ausblick A Anhang / This work describes different technical approaches to determine the aging of the chip-substrate interconnection. One of the key technologies here is the determination of the virtual junction temperature. Various possibilities for determining the virtual chip temperature of IGBTs and the aging of the chip-substrate interconnection are presented in the work and discussed with their advantages and disadvantages in terms of feasibility and applicability in the converter. Special consideration is given to the technical implementation of a measurement method based on a short-term load in the active area with subsequent determination of the cooling behavior. By comparing this with the original cooling behavior, it is possible to detect chip aging with the methods presented. Furthermore, a method is presented that enables the determination of the virtual chip temperature in the inverter via a determination of the Miller plateau height at the switch-off moment of the IGBT.:1 Einleitung 2 Alterung von Leistungshalbleitern 3 Stand der Technik der Chiptemperaturbestimmung in der Umrichterschaltung 4 Untersuchungen temperaturabhängiger elektrischer Bauelementparameter 5 Wichtige Verfahren zur Bestimmung der Chiptemperatur in der Umrichterschaltung 6 Untersuchung eines Verfahrens zur Bestimmung der Chiptemperatur in der Umrichterschaltung mittels Millerplateauhöhe 7 Technische Umsetzbarkeit der gezeigten Messverfahren 8 Zusammenfassung und Ausblick A Anhang