Silicon carbide is a very promising semiconductor material for high-power, highrequency, and high-temperature applications. SiC distinguishes from traditional narrow bandgap semiconductors, such as silicon, in that common doping impurities in SiC have activation energies larger than the thermal energy kT even at room temperature. This causes incomplete ionization of such impurities, which leads to strong temperature and frequency dependence of the semiconductor junction differential admittance and, if carrier freeze-out effects are not taken into account, errors in doping profiles calculated from capacitance-voltage data. Approaches commonly used to study the influence of incomplete impurity ionization on the junction admittance are based on the truncated space charge approximation and/or the small-signal approximation. The former leads to impurity ionization time constant and occupation number errors, while the latter fails if the measurement ac signal amplitude is larger than kT/q. In this work, a new reverse bias Schottky junction admittance model valid for the general case of an arbitrary temperature, measurement signal frequency and amplitude, and doping occupation number and time constant distributions is developed. Results of junction admittance calculations using the developed model are compared with the results of traditional models. Based on the general model, a new method of admittance spectroscopy data analysis is created and used to determine impurity parameters more accurately than allowed by traditional approaches. Incomplete impurity ionization is investigated for the case of nitrogen donors and aluminum and boron acceptors in 4H- and 6H-SiC. It is shown that the degree of carrier freeze-out is significant in heavily N-doped 6H-SiC and in Al- and B-doped SiC. Frequency dispersion of the junction admittance is shown to be significant at room temperature in N- and B-doped SiC. Junction capacitance calculations as a function of applied dc bias show that calculated doping profiles deviate from the actual impurity concentration profiles if the impurity ionization time constant is comparable with the ac signal period. This is the case for N- and B-doped SiC with certain values of the impurity activation energy and capture cross-section. Validity of the new model and its predictions are successfully tested on experimental admittance data for N- and B-doped SiC Schottky diodes.

Accurate small and large-signal models of metal-semiconductor field effect transistor (MESFET) devices are essential in all modern microwave and millimeter wave applications. Those models are used for robust designs and fabrication development. The sophistication of modern communication systems urged the need of monolithic microwave integrated circuits (MMICs), which consists of many MESFETs on the same chip. As the chip density increases, the need of accurate MESFET models becomes more pronounced. In this study, a new technique has been developed to extract a 15-element small signal model of MESFET devices. This technique implies the use of three sets of S-parameter measurements at different bias conditions. The technique consists of two major steps; in the first step, some of the bias-independent extrinsic parameters are estimated in preparation for the second step. In the second step, all other parameters should be extracted at the bias point of interest. This technique shows reliable results. Unlike other optimization techniques, our proposed technique shows insensitivity to the unavoidable measurement errors over any frequency range. It shows a unique solution for all parameter values. This technique has been tested on S-parameters of a hypothetical device model and compared with other optimization-based extraction techniques. Moreover, it has been also applied to GaAsTEK 0.8x300 μm2 MESFETs to extract the model parameters at different bias voltages. The study reveals accurate and consistent results among the similar devices on the same wafer. Some thermal characteristics of the small-signal parameters are discussed. The parameters are extracted from measurements at three temperatures for two similar devices on the same wafer. The thermal results of the two devices demonstrate consistent results, which assure the preciseness, and robustness of our proposed technique. In addition, the relation between the small-signal model parameters and the large signal model parameters is also presented. The parameters of an empirical model for the drain-source current are extracted from the dc measurements along with the small-signal transconductance and output conductance. The large-signal model results for a GaAsTEK 0.8x300 μm2 MESFET are introduced. / Ph. D.

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This dissertation presents a novel large signal modeling approach which can be used to accurately model CMOS transistors used in millimeter-wave CMOS power amplifiers. The large signal model presented in this work is classified as an empirical compact device model which incorporates temperature-dependency and device periphery scaling. These added features allow for efficient design of multi-stage CMOS power amplifiers by virtue of the process-scalability. Prior to the presentation of the details of the model development, background is given regarding the 90nm CMOS process, device test structures, de-embedding methods and device measurements, all of which are necessary preliminary steps for any device modeling methodology. Following discussion of model development, the design of multi-stage 60GHz Class AB CMOS power amplifiers using the developed model is shown, providing further model validation. The body of research concludes with an investigation into designing a CMOS power amplifier operating at frequencies close to the millimeter-wave range with a potentially higher-efficiency class of power amplifier operation. Specifically, a 24GHz 130nm CMOS Inverse Class F power amplifier is simulated using a modified version of the device model, fabricated and compared with simulations. This further demonstrates the robustness of this device modeling method.

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