There exist various models for Microwave MESFET equivalent circuit representations. These models use different mathematical models to describe the same MESFET and give similar results. However, there are some differences in the results when compared to the experimental measurements. In this thesis, various theoretical models are applied to the same MESFET and comparison made with measured data. It is shown that some models worked better on some parameters of the MESFET, while the others were more effective on other parameters. Altogether eight models were examined and data optimized to fit these theoretical models. In using optimization algorithms MATLAB FMINSEARCH and GENETIC ALGORITHM CODE were used alternatively to solve the initial value problem.

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Depuis les dix dernières années, dans les domaines liés aux transports (automobile, avionique, ferroviaire, naval), les technologies thermiques et hydrauliques tendent à laisser de plus en plus de place aux systèmes électriques. L’intérêt et le dynamisme de la Recherche en électronique de puissance se justifient par le rôle déterminant que la discipline joue au sein du développement des systèmes embarqués "plus électriques". Ce mémoire de thèse s’intéresse à l’étude de convertisseurs d’électronique de puissance, les onduleurs à source impédante, en tant que topologies alternatives aux architectures existantes au sein des systèmes de traction électrique. Plusieurs études sont établies suivant différents critères, qui, au delà d’une simple comparaison avec les architectures conventionnelles, proposent des solutions et des améliorations intervenant aussi bien dans le contrôle du système que dans sa topologie initiale. Ces études sont toutes appliquées à un système de traction électrique muni d’une machine synchrone à aimants et d’un onduleur à source impédante alimentée par une source de tension continue. Les résultats qui en découlent ont montré de larges intérêts de ces topologies concernant la maîtrise de la qualité du courant de batterie (annulation de ses ondulations hautes fréquences) mais aussi la maîtrise de certaines contraintes liées aux vieillissement des machines (possibilité de maîtriser les dv/dt). Certains inconvénients sont néanmoins établis comme le fait que la topologie n’offre guère d’amélioration du rendement (en comparaison avec les structures classiques) ou comme le fait que l’architecture rende dépendantes les commandes de l’onduleur à source impédante (côté DC) et de la machine (côté AC) / Over the past ten years, hydraulic and thermal technologies tend to make room for electrical system. Fields related to transportation (automotive, avionics, railway or naval) are directly impacted. The interest and dynamism in power electronics Research are justified by the impact of such a field in the development of embedded systems. This thesis focuses on the study of impedance-source inverters as possible topologies to replace conventional ones. Several studies are conducted according to different criteria and do not aim at only comparing the topologies. It proposes solutions and improvements in the control system as well as in its basis architecture. These studies are all applied to an electric traction system composed of an synchronous machine fed by an impedance-source inverter. It is showed that large interests come out of the obtained results. For instance, the cancellation of the high-frequency current ripples allows mastering the quality of the battery current. Moreover, some constraints as regards machine ageing can be reduced by mastering the slew rates dv/dt. Some drawbacks are nevertheless pointed out. There is no need in using such a topology to improve efficiency that is above the same as conventional structures. Moreover, controls of DC-side AC-side of the system are dependent due to the fact that inverter’s control is used to step up the DC-bus voltage

The primary goal of this research is to put into code a unique approach to addressing problems apparent with nonlinear FET models which were exposed by Calvo in her work in 1994. Since that time, the simulation software for which her model was appropriate underwent a significant update, necessitating the rewriting of her model code for a few applicable FET models in a Verilog-A, making it more compatible with the new versions of software and simulators. The problems addressed are the inconsistencies between the small-signal model and the corresponding large-signal models due to a factor called transcapacitance. It has been noted by several researchers that the presence of a nonlinear capacitor in a circuit model mathematically implies the existence of a parallel transcapacitor, if the value of its capacitance is a function of two bias voltages, the local and a remote voltage. As a consequence, simulating small signal excursions using the linear model, if the latter does not include the transcapacitance, which is inevitably present. The Calvo model attempted to improve the performance of these models by modifying terms in the charge source equations which minimize these transcapacities. Thanks to the present effort, Calvo's theory is now incorporated in the Angelov Model and can also be implemented in some other popular existing models such as Curtic, Statz and Parker Skellern models.

A novel method is shown for fitting and/or validating electro-thermal models using pulsed I(V) measurements and pulsed I(V) simulations demonstrated using modifications of an available non-linear model for an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device. After extracting the thermal time constant, good agreement is achieved between measured and simulated pulsed I(V) results under a wide range of different pulse conditions including DC, very short (<0.1%) duty cycles, and varied pulse widths between these extremes. A pulsed RF load-pull test bench was also assembled and demonstrated for a VDMOS (Vertically Diffused Metal Oxide Semiconductor) and an LDMOS power transistor. The basic technique should also be useful for GaAs and GaN transistors with suitable consideration for the complexity added by trapping mechanisms present in those types of transistors.

<p>The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. </p><p>In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current </p><p>The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.</p>

The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.

abstract: The drive towards device scaling and large output power in millimeter and sub-millimeter wave power amplifiers results in a highly non-linear, out-of-equilibrium charge transport regime. Particle-based Full Band Monte Carlo device simulators allow an accurate description of this carrier dynamics at the nanoscale. This work initially compares GaN high electron mobility transistors (HEMTs) based on the established Ga-face technology and the emerging N-face technology, through a modeling approach that allows a fair comparison, indicating that the N-face devices exhibit improved performance with respect to Ga-face ones due to the natural back-barrier confinement that mitigates short-channel-effects. An investigation is then carried out on the minimum aspect ratio (i.e. gate length to gate-to-channel-distance ratio) that limits short channel effects in ultra-scaled GaN and InP HEMTs, indicating that this value in GaN devices is 15 while in InP devices is 7.5. This difference is believed to be related to the different dielectric properties of the two materials, and the corresponding different electric field distributions. The dielectric effects of the passivation layer in millimeter-wave, high-power GaN HEMTs are also investigated, finding that the effective gate length is increased by fringing capacitances, enhanced by the dielectrics in regions adjacent to the gate for layers thicker than 5 nm, strongly affecting the frequency performance of deep sub-micron devices. Lastly, efficient Full Band Monte Carlo particle-based device simulations of the large-signal performance of mm-wave transistor power amplifiers with high-Q matching networks are reported for the first time. In particular, a CellularMonte Carlo (CMC) code is self-consistently coupled with a Harmonic Balance (HB) frequency domain circuit solver. Due to the iterative nature of the HB algorithm, this simulation approach is possible only due to the computational efficiency of the CMC, which uses pre-computed scattering tables. On the other hand, HB allows the direct simulation of the steady-state behavior of circuits with long transient time. This work provides an accurate and efficient tool for the device early-stage design, which allows a computerbased performance evaluation in lieu of the extremely time-consuming and expensive iterations of prototyping and experimental large-signal characterization. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

Electrical equivalent circuit modeling of active components is one of the most important approaches for modeling high-frequency high-power devices. Amongst the most used microwave devices, AlGaN/GaN HEMTs demonstrated their superior performance, making them highly suitable for 5G, wireless and satellite communications. Despite the remarkable performance of AlGaN/GaN HEMTs, these devices reside on substrates that invoke limitations on the operating-frequency, power-efficiency, and current dispersion phenomenon. Also, there is a limitation in present parameters extraction techniques being not able to consider both the substrate effect (Silicon, Silicon Carbide, and Diamond) and the asymmetrical GaN HEMT structure. In this thesis work, a single extrinsic parameters extraction technique using a single small-signal topology takes into account both the asymmetrical GaN HEMT structure and the different substrate types with their parasitic conduction will be developed and studied for the first time. Moreover, large-signal modeling using Quasi-Physical Zone Division technique has been applied to both GaN/D and GaN/SiC to model the isothermal-trapping free drain current, and combined with a new simple technique for comparing performance between active devices in terms of current-dispersion. The models were verified by simulating the small-signal S-parameters, large-signal IV characteristics, and single-tone load-pull. High accuracy was achieved compared to the measurement data available in the technical literature and obtained from fabricated devices.

Silicon carbide is a very promising semiconductor material for high-power, highrequency, and high-temperature applications. SiC distinguishes from traditional narrow bandgap semiconductors, such as silicon, in that common doping impurities in SiC have activation energies larger than the thermal energy kT even at room temperature. This causes incomplete ionization of such impurities, which leads to strong temperature and frequency dependence of the semiconductor junction differential admittance and, if carrier freeze-out effects are not taken into account, errors in doping profiles calculated from capacitance-voltage data. Approaches commonly used to study the influence of incomplete impurity ionization on the junction admittance are based on the truncated space charge approximation and/or the small-signal approximation. The former leads to impurity ionization time constant and occupation number errors, while the latter fails if the measurement ac signal amplitude is larger than kT/q. In this work, a new reverse bias Schottky junction admittance model valid for the general case of an arbitrary temperature, measurement signal frequency and amplitude, and doping occupation number and time constant distributions is developed. Results of junction admittance calculations using the developed model are compared with the results of traditional models. Based on the general model, a new method of admittance spectroscopy data analysis is created and used to determine impurity parameters more accurately than allowed by traditional approaches. Incomplete impurity ionization is investigated for the case of nitrogen donors and aluminum and boron acceptors in 4H- and 6H-SiC. It is shown that the degree of carrier freeze-out is significant in heavily N-doped 6H-SiC and in Al- and B-doped SiC. Frequency dispersion of the junction admittance is shown to be significant at room temperature in N- and B-doped SiC. Junction capacitance calculations as a function of applied dc bias show that calculated doping profiles deviate from the actual impurity concentration profiles if the impurity ionization time constant is comparable with the ac signal period. This is the case for N- and B-doped SiC with certain values of the impurity activation energy and capture cross-section. Validity of the new model and its predictions are successfully tested on experimental admittance data for N- and B-doped SiC Schottky diodes.