I got interested in this subject when I came in contact with Västtrafiks new paymentsystem myself during my visits in Gothenburg. I suspected problems with the informationmaterial regarding it and others seemed to share my opinion that the payment system wasdiffcult to understand. When I contacted Västtrafik and asked them about the paymentsystem they confirmed that some understanding diffculties had occurred. With thatconfirmation I decided to make it my project to look in to the matter.Some methods were used to identify the problems. The methods could again confirm thatthere were some problems with the payment system and that the information material wasa vital reason. Further research was conducted to get a more profound idea of the currentinformation material and how to make it more accessible for visitors and tourists. Theproject has been following a constant designing process to find alternative ways tocommunicate the information and make it more readable and legible with help fromseveral theories and discussions. The result became more graphic-based informationmaterial inspired with commercial – and attention principles.The purpose was to make an information material to ease the usage of Västtrafiksnew- and complicated payment system for visitors and tourists. The result of this projectwas shown to fulfill these criteria though the usability tests in the final stage of thedesigning process.

Seabased Industry AB develops system for extracting electrical energy from ocean waves with a Wave Energy Converter (WEC). The components is bought from subcontractors and then assembled into wave energy converters, buoys and marine substations by Seabased. In the future Seabased will produce more of the components themselves to reduce costs and to have better control over tolerances. The production line will also include the painting of the WECs and substations, which is performed in a painting line. The purpose of this thesis work is to study what is required to build a painting line, regarding the types of stations, transporting types and the space needed. This will result in layouts for the painting line. To receive the necessary information about production theory and corrosion and surface treatment, literature concerning this area has been studied. In addition a study visit has been done to see how a painting line may look like. This has been the basis for the solutions of the layouts. Since the design of the WEC, the production rate and the requirements of the painting system may change there are many parameters to consider. This led to several proposals of the layouts, to meet the requirements which may change. Considered the suggestions of solutions that have been presented in this report, Seabased can continue working towards developing a more optimal solution of the layout for the painting line that meets the requirements at issue.

Moore’s Law has driven a continuous demand for decreasing feature sizes used in Very Large Scale Integrated (VLSI) technology which has outpaced the solutions offered by lithography hardware. Currently, a light wavelength of 193nm is being used to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual wafer feature sizes. However, the layout which affects the printability of a circuit can be modified in a manner which can make it more lithography-friendly. In this work, we intend to implement these modifications as a series of perturbations on the initial layout generated by the CAD tool for the circuit. To implement these changes we first calculate the feature variations offline on the boundaries of all possible standard cell pairs used in the circuit layout and record them in a Look-Up Table (LUT). After the CAD tool generates the initial placement of the circuit, we use the LUT to estimate the variations on the boundaries of all the standard cells. Depending on the features which may have the highest feature variations we assign a cost to the layout and our aim is now to reduce the cost of the layout after implementing perturbations which could be a simple cell flip or swap with a neighboring cell. The algorithm used to generate a circuit placement with a low cost is Simulated Annealing which allows a high probability for a solution with a higher cost to be selected during the initial iterations and as time goes on it tends closer to the greedy algorithm. The idea here is to avoid a locally optimum solution. It is also essential to minimize the impact of the iterations performed on the initial solution in terms of wirelength, vias and routing congestion. We validate our procedure on ISCAS85 benchmark circuits by simulating dose and defocus variations using the Mentor tool Calibre LFD. We obtain a reduction of greater 20% in the number of instances with the highest cell boundary feature variations. The wirelength and the number of vias showed an increase of roughly 2.2-8.8% and 1.2- 7.8% respectively for different circuits. The routing congestion by and large remains unaffected.

Modern development of electronic devices requires the integration of more and more powerful functions within the same amount of space. However, this is accompanied by increased difficulties within the manufacturing and packaging processes. A proposal for the arrangement of wire connecting is suggested. In this work, which is to replace the multi-tier design with conventional high & long wire bonding. The advance of bonding layout of the stack die HSBGA (Heat Slug Ball Grid Array) chip assembly can enhance wire bonding with electrical performance by shortening wire length. This promises a better thermal performance of thermal consumption between the function die and heat slugs. This analysis includes simulations of electrical and thermal performance, as well as simulations of drawing layout for an actual production, the bonding looping parameters optimization, and SEM analysis to confirm the results. Based on the above analyses, the results reveal three advantages of the proposal of ¡§Advance bonding layout of chip assembly¡¨ which are: (1)reduction of 40% thermal resistance, (2)£cJC voltage insertion loss improvement of 30~40%, and (3)reduction of the gold wire length from 4.5mm to 3mm, saving 1/3 of gold wire consumption. Overall, assembly costs can be reduced by 6%.

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Thesis (M.S.)--West Virginia University, 2002. / Title from document title page. Document formatted into pages; contains vii, 76 p. : ill. Includes abstract. Includes bibliographical references (p. 72-76).

published_or_final_version / Industrial Engineering / Master / Master of Philosophy

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Advances in display technology are increasing screen size and reducing their costs. Large, wall sized screens can be found in malls, public squares and office buildings displaying photos, videos, advertising, news and announcements. The audience of large displays in public, urban environments can be constantly changing and in this thesis we investigate applying automated layout algorithms to large displays to adapt layouts to changing audiences. Abstract We review current automated layouts, discuss new challenges when applying automated layouts to large screens and present our design space for automated layouts. We investigate the human factors (such as attention, vision, and perception) and the system factors (such as display space and input devices) involved in automated layout for large displays. Abstract This thesis presents the Viewer Aware Layout (VAL) system. VAL is a system that automates the layout of images on a large display and is designed to allow many users to collectively view images. VAL, and features of VAL, are tested for engagement and it is found that there is a significant increase in agreement by users with statements describing an engaging experience when VAL is applied to an image layout. This thesis concludes with a summary of the research contributions and proposes future areas of work.