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A CMOS Variable Gain Amplifier with DC/AC Switched Control and A Low Jitter 80 MHz PLL for DVB-T ReceiversLin, Li-Pin 07 July 2005 (has links)
The first topic of this thesis presents a novel VGA (variable gain amplifier) design which is applied in the AGC (automatic gain control) loop of digital video broadcasting - terrestrial (DVB-T) receivers. A total of three digital variable gain amplifiers (DVGA) are cascaded to provide a 70 dB dynamic range and 95 MHz operation frequency. The proposed digital VGA implemented by 0.35um 2P4M CMOS technology possesses 70 dB dynamic tuning range with a 0.3 dB gain error and 95 MHz bandwidth, and the power consumption is found to be 32.7 mW given a 3.3 V power supply.
The second topic presents a design of a 60 ps peak-to-peak jitter, 80MHz, phase-locked loop (PLL) circuit for DVB-T receivers. The simulation results using the TSMC (Taiwan Semiconductor Manu-facturing Company) 0.35um 2P4M CMOS process show that the proposed PLL achieves as low as 60 ps peak-to-peak jitter when the output frequency is 80 MHz and the power consumption is merely 10.5 mW given a 3.3 V power supply.
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NTSC Digital Video Decoder and Digital Phase Locked LoopChang, Ming-Kai 12 August 2005 (has links)
The first topic of the thesis presents an NTSC digital video decoder which is designed by using two lines delay comb filter to decode the luminance signal (Y) and the chrominance signal (C). The coefficients of the low pass filter are tuned properly to reduce the gate count without losing any original performance of the chroma demodulator.
The second topic of the thesis is to propose a method and a circuitry to resolve the out-of-phase problem between the color burst and the sub-carrier in NTSC TV
receivers. The feature of the method is that a delay means is inserted which leads to
the synchronization of the color burst and the sub-carrier such that the following
color demodulator is able to extract right color signals. Besides, the locking of the
two signals will be fastened without any extra large circuit cost.
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Study of Noise Suppression and Circuit Design of a Dual Phase-Locked Loop SystemTsai, Wen-shiou 23 July 2009 (has links)
This thesis is composed of three parts. In the first part, analysis and discussion of phase noise in phase-locked loop is made. Because OFDM upconverter requires high phase noise performance, we therefore study the mechanism of noise suppression in a proposed dual phase-locked loop, and then derive the formula to predict the circuit characteristics. In the second part, experiment and simulation of a dual phase-locked loop is performed for comparison. The experiment uses hybrid circuit combined with related equipment and components to measure the noise suppression characteristics in a dual phase-locked loop. The simulation relies on the component behavioral model in ADS. Comparison between simulation and measurement shows good agreement. In the third part, this thesis carries out a 1.55¡V2.3 GHz frequency synthesizer RFIC design for DVB up-down architecture using TSMC 0.18£gm CMOS process. The test results validate the chip design.
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Phase-Locked Double-Loop Speed Regulation of a Temperature controlled FanLi, Chun-wei 24 August 2009 (has links)
Cooling fans, widely used in desktop and laptop computers, have been designed toward the tendency of low noise and low consumption power. This thesis purposes a efficient low-noise double-loop control method to regulate the fan speed according to environmental temperature. The proposed controller consists of three parts. The first part is a command generator which generates a train of pulses with its frequency varying proportionally with temperature. The second part is a phase locked loop which intends to synchronize the command pulses with the pulses fed back from the Hall IC of the motor. The third part is an inner loop quantized control that switches the fan according to the error signal sent by the phase locked loop. This double-loop design of feedback achieves accurate fan speed regulation with the nice properties of low noise and high efficiency.
The experimental results show an average regulation error of 0.4188% in the fan speed range of 306.6~1953 R.P.M which corresponds to the temperature range 10~70 Celsius.
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Design and study of phase locked loop for space applications in sub-micron CMOS technologyGhosh, Partha Pratim. January 2009 (has links)
Thesis (Ph.D.)--University of Texas at Arlington, 2009.
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Built-in self-test technique for high-speed phase-locked loops /Kim, Seongwon. January 2001 (has links)
Thesis (Ph. D.)--University of Washington, 2001. / Vita. Includes bibliographical references (leaves 68-72).
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Modelocked waveguide lasers in lithium niobate /Wessel, Rudolf. January 2000 (has links)
Thesis (doctoral)--Universität, Paderborn, 2000.
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Design of 1-V CMOS RF phase-locked loops and frequency synthesizers /Leung, Chi Tak. January 2003 (has links)
Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.
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A fractional N frequency synthesizer for an adaptive network backplane serial communication systemRangan, Giri N. K. 28 August 2008 (has links)
Not available / text
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Low-noise and high-frequency clock generation core for VLSI CMOS integrationRobinson, Moises Emanuel 28 August 2008 (has links)
Not available / text
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