In this thesis, novel multi-section laser diodes based on quantum-dot material are designed and investigated which exhibit a number of advantages such as low threshold current density; temperature-insensitivity and suppress carrier diffusion due to discrete nature of density of state of quantum-dots. The spectral versatility in the range of 1.1 µm – 1.3 µm wavelengths is demonstrated through novel mode-locking regimes such as dual-wavelength mode-locking, wavelength bistability and broad tunability. Moreover, broad pulse repetition rate tuning using an external cavity configuration is presented. A high peak power of 17.7 W was generated from the quantum-dot laser as a result of the tapered geometry of the gain section of the laser has led to successful application of such device for two-photon imaging. Dual-wavelength mode-locking is demonstrated via ground (?=1180 nm) and excited (?=1263 nm) spectral bands with optical pulses from both states simultaneously in the 5-layer quantum-dot two-section diode laser. The widest spectral separation of 83 nm between the modes was achieved in a dual-wavelength mode-locked non-vibronic laser. Power and wavelength bistability are achieved in a mode-locked multi-section laser which active region incorporates non-identical QD layers grown by molecular beam epitaxy. As a result the wavelength can be electronically controlled between 1245 nm and 1290 nm by applying different voltages to the saturable absorber. Mode-locked or continuous-wave regimes are observed for both wavelengths over a 260 mA – 330 mA current ranges with average power up to 28 mW and 31 mW, respectively. In mode-locked regime, a repetition rate of 10 GHz of optical pulses as short as 4 ps is observed. Noticeable hysteresis of average power for different bias conditions is also demonstrated. The wavelength and power bistability in QD lasers are potentially suitable for flip-flop memory application. In addition, a unique mode-locked regime at expense of the reverse bias with 50 nm wavelength tuning range from 1245 nm to 1290 nm is also presented. Broad repetition rate tunability is shown from quantum-dot external cavity mode-locked 1.27 µm laser. The repetition rate from record low of 191 MHz to 1 GHz from fundamental mode-locking was achieved. Harmonic mode-locking allows further to increase tuning up to 6.8 GHz (34th-order harmonic) from 200 MHz fundamental mode-locking. High peak power of 1.5 W can be generated directly from two-section 4 mm long laser with bent waveguide at angle of 7° at 1.14 GHz repetition rate without the use of any pulse compression and optical amplifier. Stable mode-locking with an average power up to 60 mW, corresponding to 25 pJ pulse energy is also obtained at a repetition frequency of 2.4 GHz. The minimum time-bandwidth product of 1.01 is obtained with the pulse duration of 8.4 ps. Novel tapered quantum-dot lasers with a gain-guided geometry operating in a passively mode-locked regime have been investigated, using structures that incorporated either 5 or 10 quantum dot layers. The peak power of 3.6 W is achieved with pulse duration of 3.2 ps. Furthermore, the record peak power of 17.7 W and transform limited pulses of 672 fs were achieved with optimized structure. The generation of picosecond pulses with high average power of up to 209 mW was demonstrated, corresponding to 14.2 pJ pulse energy. The improved optical parameters of the tapered laser enable to achieve nonlinear images of fluorescent beads. Thus it is for the first time that QD based compact monolithic device enables to image biological samples using two-photon microscopy imaging technique.

Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-defined radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, offset mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable effective-numberof-bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two different test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two different ways, but both of them utilized the low jitter design technique. In first test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.

This thesis presents a systematic top-down methodology for simulating a phase-locked loop using a macro model in Verilog-A. The macromodel has been used to evaluate the jitter due to supply noise, thermal noise, and ground bounce. The noise simulation with the behavioral model is roughly 310 times faster (best case) and 125 times faster (worst case). The accuracy of the model depends on the accurate evaluation of the non-linear transfer function from the various noisy nodes to the output. By modeling the noise transfer function of the circuit as closely as possible, 100% accuracy for the behavioral noise simulations compared with the HSPICE noise simulations is obtained. The macro model is written for a charge-pump phase-locked loop, but can be easily extended to other architectures. The simulations are completed using SpectreS in Cadence. The designer can use the model to estimate the jitter at the output of the PLL in a top-down design methodology or cross verify the performance of an existing chip in a bottom-up approach. / Graduation date: 2001

Graduation date: 2006 / Digital phase-locked loops (PLLs) have been receiving increasing attention recently due to their ease of integration, scalability and performance comparable to their analog counterparts. In digital PLLs, increased resolution in time-to-digital conversion is desirable for improved noise performance. This work describes the design and simulation of a stochastic time-to-digital converter (STDC) for a digital PLL to attain high resolution. The converter is intended to comprise the fine loop of the phase-frequency detector, whose coarse loop would be comprised of a time-to-digital converter designed using the conventional delay-chain approach. The STDC is designed, simulated and sent for fabrication in a 0.35μm SOI CMOS process. System level simulations in MATLAB are verified by device level simulations in Spectre on circuits extracted from layout. The results support the viability of using the proposed circuit for high resolution time-to-digital conversion.

The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts.

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the number of such challenges vary depending on the process technology employed and the end application. One such challenge that is worth mentioning is the on-chip integration of the second order passive loop filter. The area occupied by the second order passive loop filter is mainly determined by the zero determining capacitance (CZ). A low loop bandwidth CPPLL has a higher CZ value, and hence consumes a larger die area than a large loop bandwidth CPPLL. Literature survey shows that the problem of higher CZ value in low loop bandwidth CPPLL is addressed by using some form of emulation techniques. A relatively simpler emulation technique is the use of dual charge pump based loop filter. Existing dual charge pump based loop filter consume extra elements (such as summer that need opamps to realize the summer function) for achieving low CZ value. These extra elements consume extra area and additional power. We present two types of Summer-Less Dual Charge Pump (SDCP) based loop filter designs that do not need extra elements and still achieves low CZ value and this is achieved by using a second charge pump in an appropriate way. A test chip was implemented in 0.13µm UMC MMRFCMOS process to verify the presented circuits. The presented SDCP based loop filter circuits are particularly useful in designs employing multiple CPPLL’s and design employing low loop bandwidth CPPLL’s. Another challenge worth-mentioning is the frequency ranges over which the PLL can be locked. The Voltage Controlled Oscillator (VCO) of PLL mainly determines the frequency locking range of a PLL. A typical VCO has a frequency locking range of usually 1:2 to 1:3. The VCO frequency tuning range reduces with reduction in supply voltage. This poses a serious problem in low supply voltage applications that demand a wide frequency locking range, sometimes greater than 1:3. We have addressed this problem of wide PLL lock range, by using an Analog Frequency Detector. A wide frequency lock range is achieved, either by dynamically modifying the VCO or the feedback divider of PLL. Both the approaches are equally feasible. The frequency detector is used for dynamically modifying the VCO or the feedback divider of PLL. Two test chips were implemented to verify the presented Analog Frequency Detector scheme. A testchip implemented in 0.25µm CSM analog process achieves wide frequency lock range by dynamically modifying the feedback divider of PLL. Another testchip implemented in 0.13µm UMC MMRFCMOS process achieves wide frequency lock range by dynamically modifying the center frequency of the VCO. Presented analog frequency detection scheme is particularly useful in applications that demand wide PLL lock range from a single die.

The thesis uses an up-down conversion architecture to realize a wideband frequency synthesizer for digital video broadcasting (DVB) transmission system. At first, the theoretical analysis of this architecture is performed to understand the mechanism to suppress the phase noise in an optimal way. Then, the simulations using Matlab and ADS are carried out to predict the phase noise performance. Based on the above efforts, a 50 MHz ~ 1 GHz wideband frequency synthesizer hybrid circuit is implemented and its phase noise performance, corresponding to different choices of the reference sources, is finally discussed. The second part of this thesis is to extend the up-down conversion architecture to an offset phase-locked loop (PLL) architecture for wideband frequency synthesizers. The difference from the conventional offset PLLs is the phase locking of the signal at either the sum or the difference frequency of two voltage-controlled oscillators (VCOs) to the reference source for the purpose of wideband operation. The phase noise analysis of the proposed offset PLL architecture is provided. In the experiments, a 300 MHz ~ 3.6 GHz wideband frequency synthesizer hybrid circuit is implemented to verify the analyzed phase noise results. In addition, a CMOS wideband frequency synthesizer chip using the proposed offset PLL architecture has been realized. Moreover, another two CMOS wideband frequency synthesizer chips are included in this thesis. It is worth mentioning that the VCOs in these two frequency synthesizer chips use the switched capacitor and inductor techniques to achieve a wideband operation.

This thesis uses injection-locked oscillators to realize spectrum and vital sign sensor. At first, the thesis discusses the factors to affect the locking range based on Adler¡¦s equation, and adopts an increase of injection power to enlarge the locking range. Then, the circuit simulation using ADS is carried out to predict the output response of an injection-locked oscillator. As an implementation result, a CMOS chip of an injection-locked oscillator achieves 70 MHz locking range at -17.5 dBm injection power. In addition, a CMOS FM demodulator is realized with the injection-locked oscillator, showing that the chip can demodulate the FSK signal with a minimum frequency deviation of 350 KHz, a minimum input power of -39.5 dBm, and a maximum data rate of 40 Mbps. With the help of the above CMOS chips, a spectrum sensor and a vital sign sensor are realized. In the test, the spectrum sensor can measure a minimum signal power of -100 dBm at a scan speed of 100 MHz/0.5 ms, while the vital sign sensor can detect the breathing and heartbeat rate at a sensing distance of 80 cm.

The first topic of this thesis presents a novel VGA (variable gain amplifier) design which is applied in the AGC (automatic gain control) loop of digital video broadcasting - terrestrial (DVB-T) receivers. A total of three digital variable gain amplifiers (DVGA) are cascaded to provide a 70 dB dynamic range and 95 MHz operation frequency. The proposed digital VGA implemented by 0.35um 2P4M CMOS technology possesses 70 dB dynamic tuning range with a 0.3 dB gain error and 95 MHz bandwidth, and the power consumption is found to be 32.7 mW given a 3.3 V power supply. The second topic presents a design of a 60 ps peak-to-peak jitter, 80MHz, phase-locked loop (PLL) circuit for DVB-T receivers. The simulation results using the TSMC (Taiwan Semiconductor Manu-facturing Company) 0.35um 2P4M CMOS process show that the proposed PLL achieves as low as 60 ps peak-to-peak jitter when the output frequency is 80 MHz and the power consumption is merely 10.5 mW given a 3.3 V power supply.

The first topic of the thesis presents an NTSC digital video decoder which is designed by using two lines delay comb filter to decode the luminance signal (Y) and the chrominance signal (C). The coefficients of the low pass filter are tuned properly to reduce the gate count without losing any original performance of the chroma demodulator. The second topic of the thesis is to propose a method and a circuitry to resolve the out-of-phase problem between the color burst and the sub-carrier in NTSC TV receivers. The feature of the method is that a delay means is inserted which leads to the synchronization of the color burst and the sub-carrier such that the following color demodulator is able to extract right color signals. Besides, the locking of the two signals will be fastened without any extra large circuit cost.