International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / PSK demodulators have been an integral part of the signal recovery process for decades. Unless a person has designed a demodulator, how much can a person know or understand about its operation? Instruction on how to set up a demodulator’s parameters to acquire a signal is found in a manual. An explanation of why parameters are set a certain way to handle particular input signal characteristics is often not provided in a manual. This paper is designed to be a tool to aid engineers, technicians, and operators who utilize demodulators. Its purpose is to relay the functionality of a demodulator to a user so that he or she can take advantage of its control parameters and status feedback. Knowing the reasons why a demodulator is set to certain parameters may greatly reduce confusion when a system is not working properly. On site troubleshooting may be accomplished without the need to call the manufacturer of the product. Another advantage of understanding the operation will be recognized when interfacing with the manufacturer. A person will be able to relay the information to a design engineer more easily, and will understand more of the engineer’s feedback on the potential problem. Utilizing this paper as an aid to enhance operation of a PSK demodulator will bring a user one step closer to understanding the complexity of its design.

As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited channels. As a clock reconstructing module in a receiver, the recovered clock quality of Clock and Data Recovery is the main issue of the receiver performance. However, from unknown incoming jitter, it is difficult to optimize loop dynamics to minimize steady-state and dynamic jitter. In this thesis a 10 Gb/s adaptive loop bandwidth clock and data recovery circuit with on-chip loop filter is presented. The proposed system optimizes the loop bandwidth adaptively to minimize jitter so that it leads to an improved jitter tolerance performance. This architecture tunes the loop bandwidth by a factor of eight based on the phase information of incoming data. The resulting architecture performs as good as a maximum fixed loop bandwidth CDR while tracking high speed input jitter and as good as a minimum fixed bandwidth CDR while suppressing wide bandwidth steady-state jitter. By employing a mixed mode predictor, high updating rate loop bandwidth adaptation is achieved with low power consumption. Another relevant feature is that it integrates a typically large off-chip filter using a capacitance multiplication technique that employs dual charge pumps. The functionality of the proposed architecture has been verified through schematic and behavioral model simulations. In the simulation, the performance of jitter tolerance is confirmed that the proposed solution provides improved results and robustness to the variation of jitter profile. Its applicability to industrial standards is also verified by the jitter tolerance passing SONET OC-192 successfully.