This dissertation presents a unique concept for a device architecture named the nanotube (NT) architecture, which is capable of higher drive current compared to the Gate-All-Around Nanowire architecture when applied to heterostructure Tunnel Field Effect Transistors. Through the use of inner/outer core-shell gates, heterostructure NT TFET leverages physically larger tunneling area thus achieving higher driver current (ION) and saving real estates by eliminating arraying requirement. We discuss the physics of p-type (Silicon/Indium Arsenide) and n-type (Silicon/Germanium hetero-structure) based TFETs. Numerical TCAD simulations have shown that NT TFETs have 5x and 1.6 x higher normalized ION when compared to GAA NW TFET for p and n-type TFETs, respectively. This is due to the availability of larger tunneling junction cross sectional area, and lower Shockley-Reed-Hall recombination, while achieving sub 60 mV/dec performance for more than 5 orders of magnitude of drain current, thus enabling scaling down of Vdd to 0.5 V. This dissertation also introduces a novel thin-film-transistors architecture that is named the Wavy Channel (WC) architecture, which allows for extending device width by integrating vertical fin-like substrate corrugations giving rise to up to 50% larger device width, without occupying extra chip area. The novel architecture shows 2x higher output drive current per unit chip area when compared to conventional planar architecture. The current increase is attributed to both the extra device width and 50% enhancement in field effect mobility due to electrostatic gating effects. Digital circuits are fabricated to demonstrate the potential of integrating WC TFT based circuits. WC inverters have shown 2× the peak-to-peak output voltage for the same input, and ~2× the operation frequency of the planar inverters for the same peak-to-peak output voltage. WC NAND circuits have shown 2× higher peak-to-peak output voltage, and 3× lower high-to-low propagation delay times when compared to their planar counterparts. WC NOR circuits have shown 70% higher peak-to-peak output voltage, over their planar counterparts. Finally, a WC based pass transistor logic multiplexer circuit is demonstrated, which has shown more than 5× faster high-to-low propagation delay compared to its planar counterpart at a similar peak-to-peak output voltage.

Nowadays, integrated circuits (IC) are mostly implemented using Complementary Metal Oxide Semiconductor (CMOS) transistor technology. This technology has allowed the chip industry to shrink transistors and thus increase the device density, circuit complexity, operation speed, and computation power of the ICs. However, in recent years, the scaling of transistor has faced multiple roadblocks, which will eventually lead the scaling to an end as it approaches physical and economic limits. The dominance of sub-threshold leakage, which slows down the scaling of threshold voltage VTH and the supply voltage VDD, has resulted in high power density on chips. Furthermore, even widely popular solutions such as parallel and multi-core computing have not been able to fully address that problem. These drawbacks have overshadowed the benefits of transistor scaling. With the dawn of Internet of Things (IoT) era, the chip industry needs adjustments towards ultra-low-power circuits and systems. In this thesis, energy-efficient Micro-/Nano-electromechanical (M/NEM) relays are introduced, their non-leaking property and abrupt switch ON/OFF characteristics are studied, and designs and applications in the implementation of ultra-low-power integrated circuits and systems are explored. The proposed designs compose of core building blocks for any functional microprocessor, for instance, fundamental logic gates; arithmetic adder circuits; sequential latch and flip-flop circuits; input/output (I/O) interface data converters, including an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC); system-level power management DC-DC converters and energy management power gating scheme. Another contribution of this thesis is the study of device non-ideality and variations in terms of functionality of circuits. We have thoroughly investigated energy-efficient approximate computing with non-ideal transistors and relays for the next generation of ultra-low-power VLSI systems.

Ce mémoire de thèse est consacré à la mise en place d'un système opto-électronique générique basé sur une liaison toute optique bidirectionnelle de 10km. L'architecture étudiée et développée est dédiée à l'extension d'un observatoire câblé de fond de mer afin d'atteindre de nouvelles zones d'exploration. Les travaux de recherche rapportés dans ce manuscrit présentent la réalisation d'un démonstrateur, qui permet la récupération de données, issues d'un instrument connecté à un module opto-alimenté, via une seule fibre optique où transitent simultanément deux voies de données en bande C et la puissance optique d'alimentation (à 1480nm) égale à 33dBm permettant de récupérer 180mW électrique sur le module opto-alimenté.Le contexte de cette thèse de doctorat est présenté au travers d'un état de l'art sur les moyens utilisés pour l'observation des océans et sur les systèmes électroniques à faible consommation. Après un rappel des caractéristiques essentielles de l'architecture de la liaison optique préalablement établie, nous nous concentrons sur la structure opto-électronique qui a pour but d’assurer la communication entre l’observatoire et l’instrument déporté de l’extension. La définition du cahier des charges a abouti au choix du capteur (hydrophone), du débit des données (5Mbit/s) et du protocole de communication (SPI 3-fils) utilisé entre les deux modules opto-électroniques, chacun à une extrémité de la fibre optique. L'effort a été porté sur la conception d'un module opto-alimenté faible consommation (66mW) où s'intègre l'instrument. Tout au long de ce document, les choix technologiques retenus lors de la conception des deux modules opto-électroniques sont argumentés. Le banc d'essai du démonstrateur a permis de valider la conception de cette extension et d'évaluer la qualité de la transmission des données (BER inférieur à 10-6). Le fonctionnement d'un premier prototype destiné à être marinisé a été présenté au travers de la détection et de la transmission de signaux acoustiques générés en bassin d'essai. De manière à rendre le système encore plus générique, une solution alternative à base d'un FPGA, permettant l'utilisation d'une interface SPI 4-fils sans modifier la liaison optique a été présentée et validée. / This PhD thesis is devoted to the design of an opto-electrical and generic system which uses a 10km long all-optical and bidirectional link. The studied and developed system is dedicated to extend a current cabled seafloor observatory, in order to reach new exploration areas. The research work described in this thesis presents the development and the realization of a demonstrator. This later collects data from an instrument connected to its optically powered unit. The optical power supply (33dBm at 1480nm), which provides up to 180mW electrical for the optically powered unit, and the optical data in C band, are transmitted simultaneously through the same single optical fiber.The thesis context is first presented through an overview of ocean observation systems and low consumption electronic devices. After a brief review on the main characteristics of the optical architecture, we focused on the opto-electrical structure which permits the communication between the observatory and the remote instrument. The desired requirements have led us to the choice of the sensor (hydrophone), the data bit rate (5Mbit/s) and the communication protocol (SPI 3-Wire) used between both opto-electrical units, each one located at the both ends of the optical link. A special attention was devoted to the conception of the optically powered which must be low power consumption (66mW). All along this document, technical choices involved in the realization of both opto-electrical units are presented. We could evaluate the performance of the data transmission (BER less than 10-6) by using a demonstrator's test bench. Then, a first prototype designed for the ocean environment was presented through experimental measurements. Those tests were conducted in a test pool and have consisted in the detection of acoustic signals. In order to increase the range of compatible instruments, an alternative solution based on a FPGA was described and approved. This new design allows the SPI 4-Wire to be employed without any change of the current optical architecture.

Dans les dernières années, l'utilisation intensive des combustibles fossiles a déclenché une crise mondiale due à la forte production de polluants et à la réduction des stocks, en raison de sa nature de source d'énergie non renouvelable. Parce que l'utilisation généralisée des combustibles fossiles a entraîné la production de grandes quantités de CO2, ce qui est un facteur aggravant du réchauffement de la planète. Les piles à combustible microbiennes (MFC) représentent une technique de récupération d'énergie qui convertit l'énergie chimique des composés organiques en énergie électrique par le biais de réactions catalytiques de micro-organismes. La MFC peut être considérée comme un archétypique de système microbien bioélectrochimique (BES), qui exploite l’activité bio-électrocatalytique de micro-organismes vivants pour la génération de courant électrique. Durant la dernière décennie, l’évolution de l’électronique de faible consommation a rendu la technologie des MFC plus attrayante, car elle commence à pouvoir fournir une énergie comparable à celle consommée par des périphériques dit à faible consommation, comme un nœud de réseau de capteurs sans fil (WSN). En plus, les MFC ont gagné en intérêt car elles peuvent générer de l'énergie électrique tout en traitant des déchets. Contrairement aux autres piles à combustible, les MFC peuvent générer en permanence une énergie propre à une température ambiante, à la pression atmosphérique et à un pH neutre, sans entretien supplémentaire. Les seuls sous-produits sont le CO2 et H2O, qui ne nécessitent aucune manipulation supplémentaire, car le CO2 produit est biogénique, ce qui est inclus dans le cycle du carbone biogéochimique, évitant l'émission nette de carbone dans l'atmosphère. Ce manuscrit examine certains aspects liés à la technologie des piles à combustible microbiennes, depuis les réactions chimiques jusqu’aux systèmes de gestion de l'énergie requis pour exploiter la puissance fournie par les MFC. Une campagne expérimentale a été menée sur les MFCs concernant la caractérisation électrique, la connexion multiple des MFCs et l’influence des principaux paramètres qui affectent les performances de conversion de l’énergie. Le contexte de la pile à biocarburant est introduit et les principes de base de fonctionnement et les applications principales sont expliqués. L'enquête comprend une évaluation de l'impact des différents matériaux d'électrode, du substrat utilisé et des bactéries impliquées dans le processus chimique. Une perspective consiste à ajuster les paramètres afin de maximiser la production d'électricité. La conception spécifique de nos MFC de laboratoire est également présentée. Les essais expérimentaux ont été effectués sur deux types de réacteurs : la pile à combustible microbienne terrestre et la pile à combustible microbienne à eau usée. Un système de mesure approprié est présenté, il est spécialement conçu pour les tests sur les MFC. Il est capable d'assurer une mesure précise de toutes les valeurs et paramètres électriques nécessaires à la caractérisation électrique des réacteurs dans une configuration unique ou dans une connexion multiple. Les solutions utilisées pour alimenter les WWMFC étaient différentes et dans certains cas, on utilisait de vraies eaux usées, alors que dans d'autres, des solutions synthétisées appropriées étaient conçues à cet effet. Les méthodes de synthèse des solutions sont décrites. L'influence des principaux paramètres tels que le pH et la température a été analysée pour les deux types de cellules. La campagne expérimentale comprend des mesures de réacteurs en configuration unique ou disposées dans des connexions en série ou en parallèle. Les résultats confirment l'augmentation de la tension dans le cas de connexions en série et l'augmentation de la puissance dans le cas de connexions en parallèle. [...] / In recent years, the extensive use of fossil fuels has triggered into a global crisis due to high pollution and stock reduction, because of its nature of non-renewable source of energy. Because the wide use of fossil fuels has led to the production of high amounts of CO2, as a result is a trigger of the global warming issue. Microbial fuel cells (MFCs) is an energy harvesting technique that converts chemical energy from organic compounds to electrical energy through catalytic actions of microorganisms. MFC can be considered as archetypical microbial Bioelectrochemical Systems (BESs), that exploit the bio-electrocatalytic activity of living microorganisms for the generation of electric current. In the past decade, the evolution of low power electronics has made MFCs technology more attractive, because it has begun to be able to power low-power devices forming complete systems, such as the nodes of a wireless sensor network (WSN). Moreover, MFCs gained more interest because they can generate electric power while treating wastes. Unlike other fuel cells, MFCs can continuously generate clean energy at normal temperature, atmospheric pressure, and neutral pH value without any supplementary maintenance. The only by-products are CO2 and H2O, which do not require additional handling. The production of CO2 is part of a short duration carbon cycle. The CO2 produced is biogenic, which is included in the biogeochemical carbon cycle, avoiding net carbon emission into atmosphere. This manuscript examines many aspects related to microbial fuel cell technology from chemical reactions inside the cells to the energy management systems required to exploit energy delivered from MFCs for practical usage in autonomous sensors. Experimental campaign was performed on MFCs regarding electrical characterization, multiple connections of MFCs and influence of main parameters that affect energy conversion performances. The experimental tests were performed on two different lab-scale reactor typologies: terrestrial microbial fuel cell and waste water microbial fuel cell. A survey is presented about different proposed energy management systems and other devices able to build a node of a WSN powered by MFCs.

En la dècada actual, l'augment del consum energètic dels circuits integrats està tenint un impacte cada vegada més important en el disseny electrònic. Segons l'informe de la Semiconductor Industry Association de l'any 1997, es preveu que aquest impacte serà encara major en la propera dècada. En la bibliografia existeixen diversos treballs on es relaciona un consumo energètic elevat amb la degradació de les prestacions i la fiabilitat del xip. Per aquesta raó, el consum energètic ha estat incorporat com a un altre paràmetre a tenir en compte en el disseny dels circuits integrats. Es coneix com a energia de transició l'energia consumida per un circuit combinacional CMOS quan es produeix un canvi en les seves entrades. Una energia de transició excessivament elevada pot afectar a la fiabilitat del xip a través dels anomenats hot spots, i de l'electromigració. Altres efectes com el ground bouncing i la signal integrity degradation poden repercutir en les prestacions del circuit. La minimització de les degradacions esmentades anteriorment requereixen de la caracterització de l'energia de transició màxima durant la fase de disseny. A tal efecte, en aquesta tesi es proposen dues metodologies que permeten l'estimació de l'energia de transició màxima en circuits combinacionals CMOS. Donat que l'estimació del nivell màxim exacte es inviable en circuits a partir de mides mitjanes, es proposa el càlcul de dues cotes, una d'inferior i una altra de superior, que delimiten un interval de localització de l'esmentat nivell màxim. La tesi està estructurada en els següents capítols. En el capítol 1 es fa una introducció al tema investigat en aquesta tesi i es presenten els treballs existents que el tracten. En el capítol 2 s'introdueixen els models d'estimació de l'energia de transició emprats més habitualment a nivell lògic, que és el nivell de disseny considerat en aquesta tesi. Aquests models assumeixen que l'únic mecanisme de consum és la commutació de les capacitats paràsites del circuit. En els capítols 3 i 4 es tracta l'estimació de l'energia de transició màxima. Aquesta estimació es realitza a partir del càlcul de dues cotes properes, una superior i una altre inferior, a aquesta energia màxima. En el capítol 5 es presenta l'anàlisi del comportament de l'activitat ponderada front als models de retard estàtics. Finalment, en el capítol 6 s'aborden les conclusions generals de la tesis i el treball futur. / El consumo energético de los circuitos integrados es un factor cuyo impacto en el diseño electrónico ha crecido significativamente en la década actual. Según el informe de la Semiconductor Industry Association del año 1997, se prevé que este impacto será aún mayor en la próxima década. En la bibliografía existen diversos trabajos donde se relaciona un consumo energético elevado con la degradación de las prestaciones y la fiabilidad del chip. Por esta razón, el consumo energético ha sido incorporado como otro parámetro a tener en cuenta en el diseño de los circuitos integrados. Se conoce como energía de transición la energía consumida por un circuito combinacional CMOS cuando se produce un cambio en las entradas del mismo. Una energía de transición excesivamente elevada puede afectar a la fiabilidad del chip a través de los hot spots, de la electromigración. Otros efectos como el ground bouncing y la signal integrity degradation pueden repercutir en las prestaciones del circuito. La minimización de las degradaciones mencionadas anteriormente requiere de la caracterización de la energía de transición máxima durante la fase de diseño. A este efecto, se propone en esta tesis dos metodologías que permiten la estimación de la energía de transición máxima en circuitos combinacionales CMOS. Dado que la estimación del nivel máximo exacto es inviable en circuitos a partir de tamaños medios, se propone el cálculo de dos cotas, una de inferior y otra de superior, que delimiten un intervalo de localización de dicho nivel máximo. La tesis está estructurada en los siguientes capítulos. En el capítulo 1 se presenta una introducción al tema investigado en esta tesis y se resumen los trabajos existentes más importantes. En el capítulo 2 se introducen los modelos de estimación de la energía de transición más comúnmente utilizados a nivel lógico, que es el nivel de diseño considerado en esta tesis. Estos modelos asumen que el único mecanismo de consumo es la conmutación de las capacidades parásitas del circuito. En los capítulos 3 y 4 se aborda la estimación de la energía de transición máxima. Esta estimación se realiza a partir del cálculo de dos cotas cercanas, una superior y una inferior, a esta energía máxima. En el capítulo 5 se presenta el análisis del comportamiento de la actividad ponderada frente a los modelos de retardo estáticos. Finalmente, en el capítulo 6 se presentan las conclusiones generales de la tesis y el trabajo futuro. / The importance of the energy consumption on the design of electronic circuits has increased significantly during the last decade. According to the report of the Semiconductor Industry Association, of 1997, the impact in the next decade will be even greater. In the bibliography several works exist relating to the high energy consumption with the degradation of the reliability and performance of the xip. For this reason, the energy consumption has been included as another parameter to take into account during the design of integrated circuits. It is known as transition energy, the energy consumed by a CMOS combinational circuit when its inputs change their value. Excessively high transition energy may affect the reliability of the chip through the generation of hot spots and electromigration. Other effects such as ground bouncing and signal integrity degradation may reduce the performance of the circuit. In order to minimize the previously detected bad effects it is useful to characterize the maximum transition energy, during the design phase. To this objective, this thesis presents two methodologies that allow for the estimation of the maximum transition energy in CMOS combinational circuits. Given that the estimation of the maximum level is only attainable for medium size circuits, it is proposed the calculation of bounds (higher and lower) delimiting the interval where the maximum level is located. The thesis is divided into the following chapters. In chapter 1 an introduction to the topic and a review of the previous works related to this research domain is given. In chapter 2 the models most extended for the estimation of the transition energy are presented. These models are mainly used at logic level which is the level assumed in this thesis. They assume that the switching of the parasitic capacitances is the only mechanism producing energy consumption. In chapters 3 and 4 the estimation of the maximum transition energy is considered. This estimation is made from the calculation of an upper and lower bound to this maximum transition energy. In chapter 5 the analysis of the switching activity is made for different static delay models. Finally, in chapter 6 the general conclusions of the thesis and future work are discussed.

La surveillance de santé structurelle, SHM en anglais, est un domaine en plein essor avec l'arrivée massive des composites dans les transports. Ce matériau plus léger que les alliages traditionnels investit les avions, les trains, les bateaux ou les voitures. Permettant des économies substantielles d'énergie, il présente néanmoins l'inconvénient de pouvoir développer des défauts internes invisibles par une inspection visuelle. Dès lors leur surveillance est primordiale. Les pales d'avions turbopropulseurs (A400M, ATR, etc…) répondent aux mêmes exigences. Etre capable de déterminer un endommagement de la structure par le biais de capteur est tout l'enjeu des recherches. Cet objectif implique deux points : étudier le comportement de la pale et y développer un système embarqué pour obtenir des données et/ou surveiller. Dans ce contexte, ce travail de recherche a pour objectif de mener les premières études en déterminant une premier modèle comportementale des pales; en développant un premier microsystème enregistreur de paramètres de pales; en élaborant un premier algorithme de surveillance de la pale et d'événements endommageant (impacts, survitesses, survibrations) / The structural health monitoring, or SHM, represents today a key challenge today, with a massive use of composites in the field of transport. This material, lighter than a conventional alloy, is very attractive for airplanes, trains, boats or cars manufacturing. This allows significant energy savings, but can hide internal defects invisible from the outside. At this point, dedicated supervision is essential. Blades of turboprop plane (A400M, ATR, etc.) are in face of the same problems. Determination of structural defects by the use of sensors is the key solution for the research in this field. Thus, this problem has two solutions: studying blade performances and designing an embedded system able to record data and/or monitoring the structural health. The research studies presented in this thesis represent the first results of damaged blade performances. It leads to the design of a first embedded data recorder of blade parameters and computes a first dedicated algorithm for monitoring the blade structural health and damaging events (shocks, over-speeds, over-vibrations)

Thesis (PhD)-- Stellenbosch University, 2013. / ENGLISH ABSTRACT: Superconducting electronics can make the Square Kilometre Array (SKA) a better instrument. The largest radio telescope in the world will consist of several arrays, the largest of which, consisting of more than 3000 dishes, will be situated primarily in South Africa. The ambitions of the SKA are grand and their realisation requires technology that does not exist today. Current plans see signals in the band of interest ampli ed, channelised, mixed down and then digitised. An all-digital frontend could simplify receiver structure and improve its performance. Semiconductor (analog-to-digital converters) ADCs continue to make great progress and will likely nd applications in the SKA, but superconductor ADCs bene t from higher clock speeds and quantum accurate quantisation. We propose a superconducting softwarede ned radio frontend. The key component of such a frontend is a superconducting ash ADC. We show that employing such an ADC, even a small- to moderately-sized one, will signi cantly improve the instantaneous bandwidth observable by the SKA, yet retain adequate signal-to-noise ratio so as to achieve a net improvement in sensitivity. This improvement could approach factor 2 when compared to conventional technologies (at least for continuum observations). We analyse key components of such an ADC analytically, numerically and experimentally and conclude that fabrication of such an ADC for SKA purposes is certainly possible and useful. Simultaneously, we address the power requirements of high-performance computing (HPC). HPC on a hitherto unprecedented scale is a necessity for processing the vast raw data output of the SKA. Utilising the ultra-low-energy switching events of superconducting switches (certain Josephson junctions), we develop rst demonstrators of the promising eSFQ logic family, achieving experimentally veri ed shift-registers and deserialisers with sub-aJ/bit energy requirements. We also propose and show by simulation how to expand the applicability of the eSFQ design concept to arbitrary (unclocked) gates. / AFRIKAANSE OPSOMMING: Supergeleier-elektronika kan 'n beter instrument maak van die \Square Kilometre Array" (SKA). Die wêreld se grootse radioteleskoop sal bestaan uit etlike skikkings, waarvan die grootste - met meer as 3 000 skottels - hoofsaaklik in Suid-Afrika gesetel sal wees. Die SKA is ambisieus en vereis tegnologie wat nog nie vandag bestaan nie. Volgens huidige planne sal seine in die band van belang versterk, gekanalisieer, afgemeng en dan versyfer word. 'n Heel-digitale kopstuk sal die ontvangerstruktuur kan vereenvoudig en sy prestasie kan verbeter. Halfgeleier analoog-na-digital omsetters (ADOs) verbeter voortdurend en sal waarskynlik toepassings in die SKA vind, maar supergeleier ADOs trek voordeel uit hoër klok spoed en kwantumakkurate kwantisering. Ons stel 'n supergeleier sagteware-gede nieerde radio kopstuk voor. Die sleutelkomponent van so 'n kopstuk is 'n supergeleier \ ash" ADO. Ons toon hoe die gebruik van so 'n ADO, selfs een van klein tot matige bisgrootte, die oombliklike bandwydte waarneembaar deur die SKA aansienlik sal verbeter en 'n voldoende sein-tot-ruis verhouding sal behou, en gevolglik 'n netto verbetering in sensitiwiteit sal bereik. Hierdie verbetering kan, vergeleke met konvensionele tegnologie, 'n faktor van 2 nader (ten minste vir kontinuum waarnemings). Ons analiseer belangrike komponente van so 'n ADO analities, numeries and eksperimenteel en lei af dat die vervaardiging van so 'n ADO vir SKA doeleindes beide moontlik en nuttig is. Terselfdertyd spreek ons die drywingsverkwisting van Hoë-verrigting rekenaars aan. Sulke rekenaars van 'n tot dusver ongekende skaal is 'n noodsaaklikheid vir die verwerking van die enorme rou data uitset van die SKA. Deur die gebruik van die ultra-lae-energie skakels van supergeleier skakelaars (sekere Josephson-vlakke), ontwikkel ons die eerste demonstratiewe hekke van die veelbelowende eSFQ logiese familie, en toon eksperimenteel bevestigte skuifregisters en deserieëliseerders met sub-aJ/bis energievereistes. Ons stel verder voor en wys met simulasies hoe om die toepaslikheid van die eSFQ ontwerpkonsep na arbitr^ere (ongeklokte) hekke uit te brei.

This research investigates how to draw energy from a distant emanating and alternating (i.e., AC) magnetic source and deliver it to a battery (i.e., DC). The objective is to develop, design, simulate, build, test, and evaluate a CMOS charger integrated circuit (IC) that wirelessly charges the battery of a microsystem. A fundamental challenge here is that a tiny receiver coil only produces mV's of AC voltage, which is difficult to convert into DC form. Although LC-boosted diode-bridge rectifiers in the literature today extract energy from similar AC sources, they can do so only when AC voltages are higher than what miniaturized coils can produce, unless tuned off-chip capacitors are available, which counters the aim of integration. Therefore, rather than rectify the AC voltage, this research proposes to rectify the current that the AC voltage induces in the coil. This way, the system can still draw power from voltages that fall below the inherent threshold limit of diode-bridge rectifiers. Still, output power is low because, with these low currents, small coils can only extract a diminutive fraction of the magnetic energy available, which is why investing battery energy is also part of this research. Ultimately, the significance of increasing the power that miniaturized platforms can output is higher integration and functionality of micro-devices, like wireless microsensors and biomedical implants.

No / A new dual-log spiral geometry is proposed for microstrip resonators, offering substantial advantages in performance and size reduction at subgigahertz frequencies when realized in superconducting materials. The spiral is logarithmic in line spacing and width such that the width of the spiral line increases smoothly with the increase of the current density, reaching its maximum where the current density is maximum (in its center for ¿/2 resonators). Preliminary results of such a logarithmic ten-turn (2 × 5 turns) spiral, realized with double-sided YBCO thin film, showed a Q.-factor seven times higher than that of a single ten-turn uniform spiral made of YBCO thin film and 64 times higher than a copper counterpart. The insertion loss of the YBCO dual log-spiral has a high degree of independence of the input power in comparison with a uniform Archimedian spiral, increasing by only 2.5% for a 30-dBm increase of the input power, compared with nearly 31% for the uniform spiral. A simple approximate method, developed for prediction of the resonant frequency of the new resonators, shows a good agreement with the test results.

Deep Learning and Neural Networks have been studied and developed for many years as of today, but there is still a great need of research on this field, because the industry needs are rapidly changing. The new challenge in this field is called edge inference and it is the deployment of Deep Learning on small, simple and cheap devices, such as low-power microcontrollers. At the same time, also on the field of hardware design the industry is moving towards the RISC-V micro-architecture, which is open-source and is developing at such a fast rate that it will soon become the standard. A batteryless ultra low power microcontroller based on energy harvesting and RISC-V microarchitecture has been the final target device of this thesis. The challenge on which this project is based is to make a simple Neural Network work on this chip, i.e., finding out the capabilities and the limits of this chip for such an application and trying to optimize as much as possible the power and energy consumption. To do that TensorFlow Lite Micro has been chosen as the Deep Learning framework of reference, and a simple existing application was studied and tested first on the SparkFun Edge board and then successfully ported to the RISC-V ONiO.zero core, with its restrictive features. The optimizations have been done only on the convolutional layer of the neural network, both by Software, implementing the Im2col algorithm, and by Hardware, designing and implementing a new RISC-V instruction and the corresponding Hardware unit that performs four 8-bit parallel multiply-and-accumulate operations. This new design drastically reduces both the inference time (3.7 times reduction) and the number of instructions executed (4.8 times reduction), meaning lower overall power consumption. This kind of application on this type of chip can open the doors to a whole new market, giving the possibility to have thousands small, cheap and self-sufficient chips deploying Deep Learning applications to solve simple everyday life problems, even without network connection and without any privacy issue. / Deep Learning och neurala nätverk har studerats och utvecklats i många år fram till idag, men det finns fortfarande ett stort behov av forskning på detta område, eftersom industrins behov förändras snabbt. Den nya utmaningen inom detta område kallas edge inferens och det är implementeringen av Deep Learning på små, enkla och billiga enheter, såsom lågeffektmikrokontroller. Samtidigt, även på området hårdvarudesign, går industrin mot RISC-V-mikroarkitekturen, som är öppen källkod och utvecklas i så snabb takt att den snart kommer att bli standarden. En batterilös mikrokontroller med ultralåg effekt baserad på energiinsamling och RISC-V-mikroarkitektur har varit den slutliga målenheten för denna avhandling. Utmaningen som detta projekt är baserat på är att få ett enkelt neuralt nätverk att fungera på detta chip, det vill säga att ta reda på funktionerna och gränserna för detta chip för en sådan applikation och försöka optimera så mycket som möjligt ström- och energiförbrukningen. För att göra det har TensorFlow Lite Micro valts som referensram för Deep Learning, och en enkel befintlig applikation studerades och testades först på SparkFun Edge-kortet och portades sedan framgångsrikt till RISC-V ONiO.zero-kärnan, med dess restriktiva funktioner. Optimeringarna har endast gjorts på det konvolutionerande skikt av det neurala nätverket, både av mjukvara, implementering av Im2col-algoritmen, och av hårdvara, design och implementering av en ny RISC-V-instruktion och motsvarande hårdvaruenhet som utför fyra 8-bitars parallella multiplikation -och-ackumulationsoperationer. Denna nya design minskar drastiskt både slutledningstiden (3,7 gånger kortare) och antalet utförda instruktioner (4.8 gånger färre), vilket innebär lägre total strömförbrukning. Den här typen av applikationer på den här typen av chip kan öppna dörrarna till en helt ny marknad, vilket ger möjlighet att ha tusentals små, billiga och självförsörjande chip som distribuerar Deep Learning-applikationer för att lösa enkla vardagsproblem, även utan nätverksanslutning och utan någon integritetsproblematik.