Ching Lap Sze. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2006. / Includes bibliographical references (leaves 69-71). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Shuttle Mask --- p.2 / Chapter 1.2 --- Voltage Island --- p.6 / Chapter 1.3 --- Structure of the Thesis --- p.8 / Chapter 2 --- Literature Review on Shuttle Mask Floorplanning --- p.9 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.1.1 --- Problem formulation --- p.10 / Chapter 2.2 --- Slicing Floorplan --- p.10 / Chapter 2.3 --- General Floorplan --- p.11 / Chapter 2.3.1 --- Conflict Graph Approaches --- p.11 / Chapter 2.3.2 --- Integer Linear Programming Approaches --- p.14 / Chapter 2.4 --- Grid Packing --- p.15 / Chapter 2.4.1 --- "(α,β,γ)-restricted Grid Approach" --- p.15 / Chapter 2.4.2 --- Branch and Bound Searching Approach --- p.17 / Chapter 3 --- Shuttle Mask Floorplanning --- p.18 / Chapter 3.1 --- Problem Description --- p.18 / Chapter 3.2 --- An Overview --- p.20 / Chapter 3.3 --- Modified α-Restricted Grid --- p.21 / Chapter 3.4 --- Branch and Bound Algorithm --- p.23 / Chapter 3.4.1 --- Feasibility Check --- p.25 / Chapter 3.5 --- Dicing Plan --- p.30 / Chapter 3.6 --- Experimental Result --- p.30 / Chapter 4 --- Literature Review on Voltage Island Partitioning --- p.36 / Chapter 4.1 --- Introduction --- p.36 / Chapter 4.1.1 --- Problem Definition --- p.36 / Chapter 4.2 --- Dynamic Programming --- p.38 / Chapter 4.2.1 --- Problem Definition --- p.38 / Chapter 4.2.2 --- Algorithm Overview --- p.38 / Chapter 4.2.3 --- Size Reduction --- p.39 / Chapter 4.2.4 --- Approximate Voltage-Partitioning --- p.40 / Chapter 4.3 --- Quad-tree Approach --- p.41 / Chapter 5 --- Voltage Island Partitioning --- p.44 / Chapter 5.1 --- Introduction --- p.44 / Chapter 5.2 --- Problem Formulation --- p.45 / Chapter 5.3 --- Methodology --- p.46 / Chapter 5.3.1 --- Coarsening and Graph Construction --- p.47 / Chapter 5.3.2 --- Tree Construction --- p.49 / Chapter 5.3.3 --- Optimal Tree Partitioning --- p.50 / Chapter 5.3.4 --- Tree Refinement --- p.52 / Chapter 5.3.5 --- Solution Legalization --- p.53 / Chapter 5.3.6 --- Time Complexity --- p.54 / Chapter 5.4 --- Direct Method --- p.55 / Chapter 5.4.1 --- Dual Grid-partitioning Problem (DGPP) --- p.56 / Chapter 5.4.2 --- Time Complexity --- p.58 / Chapter 5.5 --- Experimental Results --- p.59 / Chapter 6 --- Conclusion --- p.66 / Bibliography --- p.69

近年來感測器、集成電路及無線通信的科技迅速發展，促使IEEE802.15工作小組6（TG6）致力硏究一個新的無線通信標準─人體區域網路（BAN）。這個新標準特別考量在人體上、人體內或人體周邊的應用。雖然BAN至今還未達成最後定案，不同類型的應用方案已被廣泛提出。這些方案可分為醫療應用（例如：生命徵象感測和植入式治療）及非醫療應用（例如：消費性電子、個人娛樂和遙遠控制）。無線感測節點〈WSN）的基本要求包括輕巧、廉價及低耗電量。因此，本論文提出了一個符合以上要求的注入式鎖態發射機。此外，我們設計了三個發射機的內部模組。由於BAN的物理層例如調變方式和頻譜配置還未完全製訂，本文的電路設計將基於IEEE802.15 TG6的初步建議。 / 第一個模組是一個利用同相位雙路輸入及電流再使用技術的次毫瓦、第一次諧波LC注入式鎖態振盪器〈ILO）。該振盪器操作範圍在醫療植入式通訊服務〈MICS）頻段，並已採用了0.13-μm CMOS工藝實現而僅佔有200 m x 380 m芯片面積。實驗結果表明，在輸入動力0 dBm時，其鎖定範圍可達800 MHz (150 950 MHz) 。最重要的是，該ILO擁有-30 dBm的高輸入靈敏度，同時在1-V供電下只消耗660 A靜態電流。超低的靜態電流使WSN能從人體收集能量而變得完全自主。 / 第二個模組是一個低功耗MICS非整數型頻率合成器，其目的在於選擇信道。雖然整數鎖相環由於其低複雜性而被廣泛使用，對MICS頻段而言並不是一項良好方案。主要原因在於其信道寬只有300 kHz，速度、頻率解析度和相位雜訊變得很難平衡。為此，我們採用0.13-μm CMOS製程設計了一個4階第二型和差積分〈Σ-）調變器分數鎖相環。為了抑制混附單頻信號，二階單迴路數字Σ-調變器加入了抖動。仿真結果顯示該頻率合成器能在15 s內鎖定，同時在1.5-V供電下只消耗4 mW功耗。 / 第三個模組是一個高效能、完全集成的E類功率放大器〈PA）。該PA採用了自給偏壓反相器作為前置放大器，操作範圍在MICS頻段及工業、科學和醫學〈ISM）頻段。在0.18-m CMOS工藝下實現的該PA佔有0.9 mm x 0.7 mm芯片面積。實驗結果表明，在1.2-V供電下及操作頻率是433 MHz時，該PA的漏極效率及輸出功率分別可達40.2 %和14.7 dBm。當操作頻率從380 MHz 到460 MHz，該PA仍能保侍最少34.7 %的漏極效率。此設計適用於低數據傳輸率、固定振幅調變，例如：QPSK、OQPSK等。 / Recent technological advances in sensors, integrated circuits and wireless communication enable miniature devices located on, in or around the human body to form a new wireless communication standard called wireless Body Area Network (BAN). Although BAN is still being investigated by the IEEE 802.15 Task Group 6 (TG6), a vast variety of applications has been proposed which can be categorized into medical applications (e.g. vital signs monitoring and implantable therapeutic treatment) and non-medical applications (e.g. consumer electronics and remote control). The basic requirements of each Wireless Sensor Node (WSN) include light weight, small form-factor, low cost and low power consumption. This thesis proposes an injection-locked transmitter which is a potential candidate to minimize the power consumption of the RF transmitter in WSNs. Three circuit blocks in the proposed injection-locked transmitter are designed and implemented. Since the physical layer of BAN, such as modulation scheme and frequency allocation, has still not been finalized yet, the prototypes in this thesis are designed based on the preliminary suggestions made by the IEEE 802.15 TG6. / The first circuit block is a sub-mW, current-reused first-harmonic LC injection-locked oscillator (ILO) using in-phase dual-input injection technique, operating in the Medical Implantable Communications Service (MICS) band from 402MHz to 405 MHz for medical implants. It has been fabricated in a standard 0.13-m CMOS technology; occupying 200 m x 380 m. Measurement results show that the proposed ILO features a wide locking range of 800 MHz (150-950 MHz) at input power of 0 dBm. More importantly, it has a high input sensitivity of -30 dBm to lock the 3-MHz bandwidth of the MICS band, while consuming only 660 W at 1-V supply. This ultra-low power consumption enables autonomous WSNs by energy harvested from the human body. / The second circuit block is a low power MICS fractional-N frequency synthesizer for channel selection. Although integer-N phase-locked loop (PLL) is widely used due to its low circuit complexity, it is not considered as a good solution for MICS band where the channel spacing is just 300 kHz, due to the severe trade-off between speed, frequency resolution and phase noise performance. To solve this issue, a 4th-order type-II Σ- fractional-N PLL is designed using a standard 0.18-m CMOS technology. A 2nd-order single-loop digital Σ- modulator with dither is designed to eliminate the spurious tones. Simulation results verify that the synthesizer achieves 15 s locking time and consumes 4 mW at a power supply of 1.5 V. / Finally, a power-efficient fully-integrated class-E power amplifier with a self-biased inverter used as a preamplifier stage has been implemented in a standard 0.18-m CMOS process, with 0.9 mm x 0.7 mm active area. It operates in both MICS band for implantable devices and Industrial, Scientific and Medical (ISM) band for wearable devices. Experimental results shows that it achieves 40.2 % drain efficiency while output power is 14.7 dBm at 433 MHz under 1.2-V supply. Moreover, the drain efficiency maintains at least 34.7 % over the frequency range from 380 MHz to 460 MHz. This design is suitable for low data-rate, constant envelope modulation, such as QPSK, OQPSK, etc. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Li, Kwan Wai. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese. / Abstract of thesis entitled: --- p.I / 摘要 --- p.IV / Contents --- p.VI / List of Figures --- p.XI / List of Tables --- p.XVII / Acknowledgement --- p.XVIII / Chapter CHAPTER 1. --- Introduction --- p.1 / Chapter 1.1 --- Motivation for body area network (BAN) --- p.1 / Chapter 1.2 --- Standardization of BAN and its positioning between different communication technologies --- p.3 / Chapter 1.3 --- Classification of BAN and its potential applications --- p.5 / Chapter 1.4 --- Requirements and challenges of BAN --- p.7 / Chapter 1.5 --- Research objectives and organization of this dissertation --- p.9 / References --- p.11 / Chapter CHAPTER 2. --- Background information of biomedical transceivers --- p.12 / Chapter 2.1 --- MICS band --- p.12 / Chapter 2.1.1 --- Frequency allocation --- p.12 / Chapter 2.1.2 --- Output power --- p.13 / Chapter 2.1.3 --- Transmit spectral mask --- p.14 / Chapter 2.1.4 --- Transmit center frequency tolerance --- p.14 / Chapter 2.1.5 --- Channel model --- p.15 / Chapter 2.1.6 --- Link budget --- p.17 / Chapter 2.2 --- Fundamental figure of merits for transceivers --- p.18 / Chapter 2.2.1 --- Noise figure, noise floor and receiver sensitivity --- p.18 / Chapter 2.2.2 --- Transmitter energy efficiency --- p.19 / References --- p.20 / Chapter CHAPTER 3. --- Review of transmitter architectures --- p.21 / Chapter 3.1 --- Overview --- p.21 / Chapter 3.2 --- Architectures --- p.22 / Chapter 3.2.1 --- Quadrature --- p.22 / Chapter 3.2.2 --- Polar --- p.23 / Chapter 3.2.3 --- PLL-based --- p.24 / Chapter 3.2.4 --- Injection-locked --- p.26 / Chapter 3.3 --- Radio architecture selection for biomedical systems in BAN --- p.27 / Chapter 3.3.1 --- Data-rate --- p.27 / Chapter 3.3.2 --- Modulation scheme --- p.28 / Chapter 3.3.3 --- Proposed transmitter architecture --- p.28 / References --- p.31 / Chapter CHAPTER 4. --- Design of sub-mW injection-locked oscillator --- p.33 / Chapter 4.1 --- Introduction --- p.34 / Chapter 4.2 --- Circuit design and analysis --- p.34 / Chapter 4.3 --- Experimental results --- p.47 / Chapter 4.4 --- Summary --- p.55 / References --- p.56 / Chapter CHAPTER 5. --- Design of low-power fractional-N frequency synthesizer --- p.58 / Chapter 5.1 --- Synthesizer architectures --- p.59 / Chapter 5.2 --- PLL design fundamentals --- p.63 / Chapter 5.2.1 --- Stability --- p.63 / Chapter 5.2.2 --- Phase noise --- p.65 / Chapter 5.3 --- Proposed architecture --- p.67 / Chapter 5.4 --- System design --- p.68 / Chapter 5.4.1 --- Stability --- p.68 / Chapter 5.4.2 --- Phase noise --- p.73 / Chapter 5.5 --- Σ modulation in fractional-N synthesis --- p.75 / Chapter 5.5.1 --- Basic operating principles --- p.76 / Chapter 5.5.2 --- An accumulator as a first-order Σ- modulator --- p.78 / Chapter 5.5.3 --- Noise analysis --- p.80 / Chapter 5.5.4 --- Architectures --- p.84 / Chapter 5.5.5 --- Design and modeling --- p.87 / Chapter 5.5.6 --- Digital circuit implementation --- p.99 / Chapter 5.5.7 --- Measurement results --- p.104 / Chapter 5.6 --- Time domain behavioral modeling --- p.104 / Chapter 5.7 --- Design of building blocks --- p.106 / Chapter 5.7.1 --- VCO --- p.107 / Chapter 5.7.1.1 --- Principles --- p.107 / Chapter 5.7.1.2 --- Circuit design --- p.111 / Chapter 5.7.2 --- PFD --- p.131 / Chapter 5.7.2.1 --- Principles --- p.131 / Chapter 5.7.2.2 --- Circuit design --- p.133 / Chapter 5.7.3 --- CP --- p.136 / Chapter 5.7.3.1 --- Principles --- p.136 / Chapter 5.7.3.2 --- Circuit design --- p.137 / Chapter 5.7.4 --- Frequency divider --- p.138 / Chapter 5.7.4.1 --- Principles --- p.138 / Chapter 5.7.4.2 --- Circuit design --- p.145 / Chapter 5.7.5 --- Loop filter --- p.148 / Chapter 5.8 --- Layout issues --- p.149 / Chapter 5.9 --- Overall simulation results --- p.150 / Chapter 5.1 --- Summary --- p.152 / References --- p.153 / Chapter CHAPTER 6. --- Design of high-efficient power amplifier --- p.154 / Chapter 6.1 --- Classification of PAs --- p.154 / Chapter 6.2 --- Circuit design considerations --- p.158 / Chapter 6.3 --- Experimental results --- p.160 / Chapter 6.4 --- Summary --- p.164 / References --- p.166 / Chapter CHAPTER 7. --- Conclusions and future work --- p.167 / Chapter 7.1 --- Conclusions --- p.167 / Chapter 7.2 --- Future work --- p.168 / References --- p.171

Noninvasive pulse oximetry represents an area of potential interest to the army, because it could provide cost-effective, safe, fast and real-time physiological assessment in a combat injured soldier. Consequently, there is a need to develop a reliable, battery-powered, wearable pulse oximeter to acquire and process photoplethysmographic (PPG) signals using an optimized sensor configuration. A key requirement in the optimal design of a wearable wireless pulse oximeter is low power management without compromising signal quality. This research investigated the advantage gained by increasing the area of the photodetector and decreasing the light emitting diode (LED) driving currents to reduce the overall power requirement of a reflectance mode pulse oximeter sensor. In vitro and preliminary in vivo experiments were conducted to evaluate a multiple photodetector reflectance sensor setup to simulate a varying detection area. It was concluded that a reflection pulse oximeter sensor employing a large area photodetector is preferred over a similar transmission type sensor for extending the battery life of a wireless pulse oximeter intended for future telemedicine applications.

Aplicações móveis que não podem ser recarregadas durante operação, como sensores biomédicos e aplicações da Internet das Coisas, dependem da extração de energia do próprio meio onde se encontram. Tensões de alimentação típicas são normalmente maiores que as disponiveis por métodos de extração de energia do meio e requerem uma conversão de nivel DC que invariavelmente resulta em perdas proporcionais ao fator de conversão. Consequentemente, aplicações projetadas para tensões de alimentação mais próximas da tensão nominal da fonte melhora a eficiência energética. Entretanto, topologias de circuitos elétricos para tensões típicas de alimentação sao impróprias para tensões extremamente baixas. Neste trabalho foram propostas topologias de amplificadores de saída unipolar e diferencial para tensões de alimentaçãoo na casa de centenas de milivolts. As técnicas propostas se baseiam no uso de pares pseudodiferenciais com terminais de corpo polarizados diretamente para vários propósitos, incluindo rejeição de modo comum e polarização de modo comum de saída e corrente DC. Adicionalmente, um oscilador baseado na mesmas técnicas de polarização foi proposto e projetado para duas classes de aplicações: um oscilador de referência intrinsicamente estável e um oscilador controlado por tensão para conversão analógica-digital com melhor linearidade. / Nomadic applications which cannot be recharged while at operation, such as biomedical sensors and Internet of Things applications, rely on energy harvesting from the environment. Typical supply voltages are usually higher than those achieved by energy harvesting methods and requires DC-DC conversion levels, which invariably results in energy loss proportionally to the step of voltage conversion. Consequently, designing at supply voltages closer to the nominal voltage of the energy source improves power efficiency. However, extremely low supply voltages bring design challenges, as circuit topologies for typical voltages employ techniques not suitable for extremely low supply voltages. In this work, single ended and fully differential amplifier topologies for voltage supplies in the range of few hundreds mV were proposed. The proposed approaches use the pseudo differential pairs with the transistor bulk terminals with forward biasing voltages for several purposes, including common mode rejection, output common mode voltage and DC current biasing. Additionally, a ring oscillator based in the same biasing techniques was proposed and designed for two main classes of applications: an intrinsically stable reference oscillator and a voltage controlled oscillator for analog-digital conversion with linearity improvements.

Desde os anos 80 a evolução dos processos de fabricação de circuitos integrados MOS tem buscado a redução da tensão de alimentação, como forma de se reduzir o consumo de energia dos circuitos. Partiu-se dos antigos 5 V, padrão estabelecido pela lógica TTL nos anos 70, até os circuitos modernos que operam com alimentação pouco abaixo de 1 V. Entretanto, desde os primeiros anos da década de 2000, a tensão de alimentação está estabilizada neste patamar, devido a limitações tecnológicas que tem se mostrado difíceis de serem transpostas. Tal desafio tem sido estudado por grupos de pesquisa ao redor do mundo, e diversas estratégias tem sido propostas para se chegar a circuitos analógicos e digitais que operem sob tensão de alimentação bem inferior a 1 V. De fato estes grupos têm focado seus estudos em circuitos que operam com tensão de alimentação inferior a 0,5 V, alguns chegando à casa de 200 ou 100 mV, ou até menor. Dentre as diversas classes de circuitos, os conversores de dados dos tipos digital-analógico (DAC) e analógicodigital (ADC) são circuitos fundamentais ao processo de integração entre os módulos que processam sinais analogicamente e os que processam sinais digitalmente, sendo assim essenciais à implementação dos complexos SoCs (System-on-Chips) da atualidade. Este trabalho apresenta um estudo sobre o desempenho da configuração MOSFET em rede M-2M (similar à rede R-2R que emprega resistores), utilizada como circuito conversor digital-analógico, quando dimensionada para operar sob tensão de alimentação muito baixa, da ordem de 200 mV ou inferior. Tal estudo se baseia no emprego de um modelo para os MOSFETs que é contínuo desde a condição de inversão fraca (subthreshold) até a inversão forte, e inclui o uso de um modelo de descasamento entre MOSFETs que é válido para qualquer condição de operação. Com base neste estudo foi desenvolvida uma metodologia de projeto, capaz de estabelecer as relações de compromisso entre “tensão de alimentação”, “resolução efetiva” e “área ocupada em silício”, fundamentais para se atingir um circuito otimizado. Resultados de simulação elétrica são apresentados e confrontados com os resultados analíticos, visando a comprovação da metodologia. O circuito já foi enviado para fabricação, e deve começar a ser testado em breve.

電源管理集成電路被廣泛應用於便攜式電子應用。在同一芯片需要不同的電源電壓水平。由於芯片尺寸，工作速度和所需功耗的要求，低壓差穩壓器（LDO）在快遞瞬態響應，低噪聲，以及高精度的電子產品中具有廣泛的應用。 / LDO的負載瞬間變化取決於功率金氧半場效電晶體的大小、偏置電流和誤差放大器的增益。檢測輸出電壓，並使用大電容和電阻通過電容耦合，增加偏置電流是一個簡單的方法來改善負載瞬間變化。然而，電阻電容佔據較大的芯片面積。 / 權衡功耗和芯片尺寸，本論文中提出用數字檢測電路取代用於瞬態耦合的大電容和電阻。所提出的電路是讓功率金氧半場效電晶體的栅極電容電流增加充電或放電，以提高LDO的負載瞬間響應速度。產生這種電流通過檢測內部的變化，並產生一個電壓脈衝控制迴轉電流，然後通過使用一組數字電路去改變充電或放電的電量。 / 擬議的設計已在UMC0.18微米 CMOS制程技術實現。LDO的輸入電壓為0.9伏至1.3伏和穩壓0.7伏。最大輸出電流為50豪安。經過測量，負載瞬間變化得到改善。負載瞬間的響應時間可以從75微秒（傳統）減少到75納秒。 / Power-management IC is widely used in portable electronic applications. Different supply voltage levels are required in the same chip. Due to the size, speed and power requirements, low-dropout regulator (LDO) is generally adopted for applications which need fast transient response, low noise and high accuracy. / Transient response of a LDO is limited by the size of power MOSFET, biasing current and gain of error amplifier. Detecting the output voltage and using large RC components for capacitive coupling to increase the biasing current is a straightforward method to improve the transient response. However, this requires a large chip size for the RC components. / By considering power consumption and size, digital detection circuit is proposed to replace the large capacitors and resistors used for transient coupling. The proposed circuit is to increase the charging or discharging current to the gate of the power MOSFET to increase the transient speed of LDO. This current is generated by detecting the internal changes and generating a voltage pulse to control the slewing current by using a set of digital circuit. / The proposed design has been realized in UMC 0.18μm CMOS technology. The input voltage of the LDO is 0.9 to 1.3V and the regulated voltage is 0.7V. The maximum output current is 50mA. From the measurement, the transient response is improved. The response time due to load transient changes can be reduced from 75s (conventional) to 75ns. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Kwong, Ka Yee. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references. / Abstracts also in Chinese. / Abstract / Acknowledgments / Table of Content / List of Figures / List of Tables / Chapter Chapter 1 --- LDO regulator research background / Introduction / Chapter Section 1.1 --- Generic LDO regulator structure / Chapter Section 1.2 --- Principle of LDO regulator operation / Chapter Section 1.3 --- Specifications / Chapter References / Chapter Chapter 2 --- Review of state-of-the-art transient-improvement techniques for LDO regulators / Introduction / Chapter Section 2.1 --- Slew rate improvement at power transistor gate / Chapter Section 2.2 --- Frequency compensation / Chapter Section 2.3 --- Short summary / References / Chapter Chapter 3 --- A proposed output-capacitorless LDO regulator with digital voltage spike detection / Chapter Introduction / Chapter Section 3.1 --- LDO regulator core structure / Chapter Section 3.2 --- Digital switches based LDO regulator / Chapter Section 3.3 --- LDO regulator with proposed digital voltage spike detection circuit / Chapter Section 3.4 --- Simulation result / Chapter Section 3.5 --- Short summary / References / Chapter Chapter 4 --- Measurement results / Introduction / Chapter Chapter 5 --- Conclusion and Future Work

So Pui Tak. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references. / Abstracts in English and Chinese. / Abstract --- p.ii / Acknowledgement --- p.v / Table of Contents --- p.vi / List of Figures --- p.ix / List of Tables --- p.xii / Chapter Chapter 1 --- Introduction --- p.11 / Chapter 1.1 --- Overview --- p.1-1 / Chapter 1.1 --- Power Consumption in Conventional CMOS circuit --- p.1-1 / Chapter 1.2 --- Power Consumption in Synchronous Circuit --- p.1-6 / Chapter 1.4 --- Objectives --- p.1-7 / Chapter 1.5 --- Thesis Outline --- p.1-8 / Chapter Chapter 2 --- Background Theory --- p.2-1 / Chapter 2.1 --- Introduction --- p.2-1 / Chapter 2.2 --- Definition of Adiabatic Principle --- p.2-1 / Chapter 2.3 --- Overview of Adiabatic Circuit --- p.2-3 / Chapter 2.4 --- Asynchro nous Circuits --- p.2-7 / Chapter Chapter 3 --- Adiabatic Circuit usingRVS --- p.3-1 / Chapter 3.1 --- Introduction --- p.3-1 / Chapter 3.2 --- Architecture --- p.3-2 / Chapter 3.3 --- Ramp Voltage Supply Generator --- p.3-4 / Chapter 3.4 --- Circuit Evaluation --- p.3-7 / Chapter 3.5 --- Simulation Results --- p.3-8 / Chapter 3.4 --- Experimental Results --- p.3-9 / Chapter Chapter 4 --- Asynchronous Circuit Technique --- p.4-1 / Chapter 4.1 --- Introduction --- p.4-1 / Chapter 4.2 --- Architecture --- p.4-1 / Chapter 4.2.1 --- Muller Distributor Block Design --- p.4-2 / Chapter 4.2.2 --- Delay Block Design --- p.4-4 / Chapter Chapter 5 --- Adiabatic -Asynchronous Multiplier --- p.5-1 / Chapter 5.1 --- Introduction --- p.5-1 / Chapter 5.2 --- Combination of Adiabatic and Asynchronous Techniques. --- p.5-1 / Chapter 5.3 --- Oscillator Block Design --- p.5-3 / Chapter 5.4 --- Multiplier Architecture --- p.5-6 / Chapter Chapter 6 --- Layout Consideration --- p.6-1 / Chapter 6.1 --- Introduction --- p.6-1 / Chapter 6.2 --- Floorplanning --- p.6-1 / Chapter 6.3 --- Routing Channels --- p.6-2 / Chapter 6.3 --- Power Supply --- p.6-4 / Chapter 6.4 --- Input Protection Circuitry --- p.6-5 / Chapter 6.5 --- Die Micrographs of the Chip --- p.6-7 / Chapter Chapter 7 --- Simulation Results --- p.7-1 / Chapter 7.1 --- Introduction --- p.7-1 / Chapter 7.2 --- Muller Distributor Control Signal --- p.7-1 / Chapter 7.3 --- Power Consumption --- p.7-6 / Chapter 7.3.1 --- Synchronous Multiplier --- p.7-6 / Chapter 7.3.2 --- AAT Multiplier --- p.7-7 / Chapter 7.3.3 --- Power Comparison --- p.7-8 / Chapter Chapter 8 --- Measurement Results --- p.8-1 / Chapter 8.1 --- Introduction --- p.8-1 / Chapter 8.2 --- Experimental Setup --- p.8-2 / Chapter 8.3 --- Measurement Results --- p.8-6 / Chapter Chapter 9 --- Conclusion --- p.9-1 / Chapter 9.1 --- Contributions --- p.9-1 / Chapter Chapter 10 --- Bibliography --- p.10-1 / Appendix I Building Blocks --- p.1 / Appendix II Simulated Waveform --- p.7 / Appendix III Measured Waveform --- p.8 / Appendix IV Pin List --- p.9

In measurement, the entire BBP design with the proposed gate-level structures exhibits high robustness in power supply and frequency variations. It can function normally at a minimum of 0.33 V power supply, which is over 100 mV below typical threshold voltage. In the test of the ACRL circuits, the ACRL cells show 30 - 70% delay reduction when compared to the standard static CMOS cells. And the ACRL custom PIE decoder works at the minimum of 0.26 V power supply, which is 40 mV lower than the minimum operating voltage archived by the PIE decoder in the BBP implemented with standard cells. / In this thesis, methodologies and examples are proposed for subthreshold digital circuit design. There is also a full study on subthreshold characteristics of devices and circuits in very-low-voltage operation. The EPC C1G2 baseband processor (BBP) for passive UHF (ultra high frequency) RFID (radio frequency identification) tag is selected as a subthreshold design example, as it is a digital design typified with instable very low supply voltage and requires ultra low power in operation. To tailor the BBP for lower operating voltage in subthreshold region, optimized structures and topologies are proposed in different hierarchical levels. In the system view, the BBP is partitioned according to the clock domain and the constraints of timing. Go down to the RTL and gate level, pipelining, parallelism, clock gating and one-hot state transition are implemented in the logic design according to the actual requirement. In this way energy awareness and power saving are achieved with enhanced robustness to operate in subthreshold region. The BBP with the proposed logic structures has been fabricated in several deep submicron CMOS technologies. Transistor level design is the bottom level for IC designers, the proposed active control ratioed logic (ACRL) is a logic style with fast pull-up network and less capacitance, particularly suitable for the implementation of high fan-in AOI-familiar (and-or-inverter) structure. Some general ACRL cells designs, 32-bit equality comparator and, a custom PIE decoder with ACRL cells, which is the important block of BBP with critical timing, have been fabricated in 130 nm CMOS technology. / Subthreshold designs are required in many actual applications. Especially, the subthreshold digital systems and circuits have become more and more popular in portable devices and passive systems. In conception subthreshold digital circuits are very-low-voltage circuits, they have great reduction of power consumption but suffer from long logic delay as the driving current for logic transition and propagation is greatly reduced. / Shi, Weiwei. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 146-152). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

In addition, we can further reduce the power consumption by reducing the number of interconnects. We propose to use a quaternary (4-level) logic output to replace the binary (2-level) logic output, which will reduce the number of interconnect by half. A 6-bit current mode analog-to-quaternary converter (AQC) test chip is designed with special current mode quaternary logic functions. / The power reduction techniques are carried out in both circuit and system levels. At the circuit level, a new sub-stage design using voltage comparator is proposed to reduce power consumption without any performance degradation. At the system level, we observe that the signal-to-noise ratio (SNR) of a current mode pipelined ADC is proportional to the input current level, and the SNR of a pipelined ADC is dominated by the first few stages. Thus, it is possible to reduce the power consumption without significantly degrading the SNR by gradually reducing the current level of each stage along the pipeline. A 12-bit CMOS current mode pipelined ADC test chip is designed with a 0.35mum CMOS digital process. The measured signal-to-noise and distortion ratio (SNDR), spurious free dynamic range (SFDR) and total harmonic distortion (THD) are 64.90dB, 67.79dB and -67.02dB, respectively. The effective number of bit (ENOB) achieved is 10.49-bit and the calculated FOM is 1.31pJ, which has the lowest power consumption among reported current mode ADCs. / The supply voltage of advanced CMOS technology is reduced to 1V or less. It is very difficult to design high performance analog circuit at this supply voltage because of the limited dynamic range. One possible solution is to use current mode circuit technique which is less sensitive to the limited dynamic range. Moreover, current mode circuit is more suitable for low voltage applications compare to the conventional voltage mode circuit. This research uses analog-to-digital converter (ADC) as a vehicle to investigate current mode design techniques with a main focus on power reduction. / Chan Chi Hong. / "September 2007." / Adviser: C. F. Chan. / Source: Dissertation Abstracts International, Volume: 69-08, Section: B, page: 4923. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Ma, Qiang. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 78-80). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Background --- p.1 / Chapter 1.2 --- Floorplanning --- p.2 / Chapter 1.3 --- Motivations --- p.4 / Chapter 1.4 --- Design Implementation of Voltage Islands --- p.5 / Chapter 1.5 --- Problem Formulation --- p.8 / Chapter 1.6 --- Progress on the Problem --- p.10 / Chapter 1.7 --- Contributions --- p.12 / Chapter 1.8 --- Thesis Organization --- p.14 / Chapter 2 --- Literature Review on MSV --- p.15 / Chapter 2.1 --- Introduction --- p.15 / Chapter 2.2 --- MSV at Post-floorplan/Post Placement Stage --- p.16 / Chapter 2.2.1 --- """Post-Placement Voltage Island Generation under Performance Requirement""" --- p.16 / Chapter 2.2.2 --- """Post-Placement Voltage Island Generation""" --- p.18 / Chapter 2.2.3 --- """Timing-Constrained and Voltage-Island-Aware Voltage Assignment""" --- p.19 / Chapter 2.2.4 --- """Voltage Island Generation under Performance Requirement for SoC Designs""" --- p.20 / Chapter 2.2.5 --- """An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning""" --- p.21 / Chapter 2.3 --- MSV at Floorplan/Placement Stage --- p.22 / Chapter 2.3.1 --- """Architecting Voltage Islands in Core-based System-on-a- Chip Designs""" --- p.22 / Chapter 2.3.2 --- """Voltage Island Aware Floorplanning for Power and Timing Optimization""" --- p.23 / Chapter 2.4 --- Summary --- p.27 / Chapter 3 --- MSV Driven Floorplanning --- p.29 / Chapter 3.1 --- Introduction --- p.29 / Chapter 3.2 --- Problem Formulation --- p.32 / Chapter 3.3 --- Algorithm Overview --- p.33 / Chapter 3.4 --- Optimal Island Partitioning and Voltage Assignment --- p.33 / Chapter 3.4.1 --- Voltage Islands in Non-subtrees --- p.35 / Chapter 3.4.2 --- Proof of Optimality --- p.36 / Chapter 3.4.3 --- Handling Island with Power Down Mode --- p.37 / Chapter 3.4.4 --- Speedup in Implementation and Complexity --- p.38 / Chapter 3.4.5 --- Varying Background Chip-level Voltage --- p.39 / Chapter 3.5 --- Simulated Annealing --- p.39 / Chapter 3.5.1 --- Moves --- p.39 / Chapter 3.5.2 --- Cost Function --- p.40 / Chapter 3.6 --- Experimental Results --- p.40 / Chapter 3.6.1 --- Extension to Minimize Level Shifters --- p.45 / Chapter 3.6.2 --- Extension to Consider Power Network Routing --- p.46 / Chapter 3.7 --- Summary --- p.46 / Chapter 4 --- MSV Driven Floorplanning with Timing --- p.49 / Chapter 4.1 --- Introduction --- p.49 / Chapter 4.2 --- Problem Formulation --- p.52 / Chapter 4.3 --- Algorithm Overview --- p.56 / Chapter 4.4 --- Voltage Assignment Problem --- p.56 / Chapter 4.4.1 --- Lagrangian Relaxation --- p.58 / Chapter 4.4.2 --- Transformation into the Primal Minimum Cost Flow Problem --- p.60 / Chapter 4.4.3 --- Cost-Scaling Algorithm --- p.64 / Chapter 4.4.4 --- Solution Transformation --- p.66 / Chapter 4.5 --- Simulated Annealing --- p.69 / Chapter 4.5.1 --- Moves --- p.69 / Chapter 4.5.2 --- Speeding up heuristic --- p.69 / Chapter 4.5.3 --- Cost Function --- p.70 / Chapter 4.5.4 --- Annealing Schedule --- p.71 / Chapter 4.6 --- Experimental Results --- p.71 / Chapter 4.7 --- Summary --- p.72 / Chapter 5 --- Conclusion --- p.76 / Bibliography --- p.80