Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2007. / Includes bibliographical references (leaves 83-85). Also available in electronic version.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007. / Allen, Mark, Committee Chair ; Brand, Oliver, Committee Member ; Kenney, James, Committee Member ; Hesketh, Peter, Committee Member ; Michaels, Jennifer, Committee Member.

University of Macau / Faculty of Science and Technology / Department of Electrical and Computer Engineering

Organic thin-film transistors (OTFTs) have been widely studied because of their promising potential for application in low-cost, large-area and flexible electronics. However, several challenges remain on the way towards practical OTFT devices, such as a high operating voltage (> 20 V) induced by the low charge carrier mobility of organic semiconductors and low capacitance of organic gate dielectrics. A low operating voltage is essential for various OTFTs applications, such as portable displays, radio frequency identification tags (RFIDs), smart textiles and sensors. The key to low voltage operation of OTFTs is reduction of the threshold voltage, inverse subthreshold slope which can be fulfilled by using a high-capacitance gate dielectric with superior interface properties. Since field-effect current is proportional to field-induced charge density, using a gate dielectric layer with high dielectric constant (high-k) enhances output current densities at much lower applied voltages. Very thin dielectric layers have reportedly suffered from poor dielectric properties, while very high-k gate dielectrics have led to inferior dielectric-semiconductor interface. As a result, unsatisfactory device performance, such as low charge carrier mobility and high gate leakage current, has been obtained. In addition, solution-processability on a variety of substrates and compatibility with most common semiconducting materials make high-k dielectric materials an unrivalled candidate for low-voltage, low-cost applications. Consequently, the aim of this project was to produce a high-quality, high-capacitance gate dielectric with excellent properties which is consistent with cheap, basic solution-processing manufacturing techniques. With great promise in hybrid materials, a novel, high-k dielectric material based on alternative organic-inorganic nanocomposites that combine very high dielectric constant values intrinsic to ferroelectric ceramic materials (nanoparticles) with mechanical flexibility, low-cost and easy processing of polymers was developed. Both low- and high-k polymer matrices have been used in formulating high-k nanocomposite dielectric suspensions. The uniformity of suspensions has been improved by surface modification of nanoparticles in the case of low-k polymers, while a combination of polymer choice, solvents and nanoparticle-to-polymer ratio led to homogenous suspensions based on high-k polymers. The nanocomposite preparation technique was also unique to this work and gave reproducibly stable nanocomposite suspensions. Finally, ultralow-voltage (~ 1) OTFTs have been successfully demonstrated by integrating nanocomposite bilayer dielectrics using a high-k fluorinated polymer. Bilayer dielectrics were formed by (partially) capping the surface of the nanocomposite films with an ultrathin capping layer. The capping layer was the key to the operation of low-voltage OTFTs as it allowed remarkable and advantageous use of the nanocomposite surface roughness while improving the dielectric-semiconductor surface roughness. Ultimately, such nanocomposite bilayers have a potential to pave the way towards low-cost fabrication and integration of low-voltage components and circuits on flexible substrates.

This thesis presents techniques to implement analog-to-digital converters (ADCs) under an ultra-low-supply-voltage of 0.2 V to reduce the power consumption. The thesis proposes a dynamic bulk biasing circuit to adjust the PMOS bulk voltage to balance the NMOS and PMOS drain currents to guarantee functionality in the presence of process, voltage, and temperature variations. The dynamic bulk bias circuit is analyzed rigorously to show its functionality. This thesis also describes a new comparator suitable for a 0.2-V supply using ac-coupling, stacked input pairs, and voltage-boosted load capacitor. A 10-bit 5-kS/s successive-approximation-register (SAR) ADC in a 180-nm CMOS process with a supply voltage of 0.2 V demonstrates these ideas. The ADC exhibits a differential nonlinearity (DNL) and integral nonlinearity (INL) within +0.42/-0.45 and +0.62/-0.67 LSB, respectively. The measured SFDR and SNDR at 5 kS/s with a Nyquist-frequency input are 65.9 dB and 52.1 dB, respectively. The entire ADC and dynamic bulk biasing circuitry consume 22 nW including leakage power to yield a figure-of-meirt (FoM) of 8.8 fJ/conv.-step. Measurements of multiple chips show the proposed dynamic bulk biasing fully recovers the ADC performance when the supply voltage is varied. The nW power consumption makes the design well suited for wireless sensor node and energy harvester applications.

With the growing acceptance of photovoltaic (PV) systems globally including Sweden, an increasing number of PV systems has continually been installed all through Sweden. In this study, a selected residential area in Uppsala Sweden is considered as a possible site for PV system installation. Due to the intermittent nature of this energy source and the disturbances it causes to the grid, there is therefore the need to determine the amount of PV that can be accommodated by the already existing grid without any adverse effect to it. This is known as hosting capacity (HC). The HC signifies the level of risks the network operator as well as customers are willing to take with regard to the stability of the grid network. Many possibilities exist by which this can be done which are well discussed later in this report. However, the deterministic method is used in this work. For an effective determination of the HC, the DIgSILENT Power Factory 2021 is used to simulate a synthetic network assumed to be similar to that of the area studied. A parametric analysis is also done to as certain the impact some network variables would have on the limit of PV systems a grid network can accommodate. The results of the study showed that under 0 % penetration, the grid network is stable and no violations witnessed neither from the network with 800 kVA transformer considered as the main network in this study nor that with 500 kVA used for the parametric studies. However, the loadings on the two transformers varied by about 15 %. Integrating PVs into the grid network introduced some level of instability which increases as the size of the PVs increases. This shows the need to peg the PVs’ size to a certain maximum to be able to have control over the grid network. Customers are allowed to install lower sizes but not more than this maximum. The results also showed that changing the transformer size do not affect the nodal voltages nor the cable loadings in the network provided all other parameters remained the same. The only impact is on the transformer loading, with smaller transformers experiencing higher loading condition. This study serves as a basis to determine the initial range of PV sizes customers are allowed to install in the area studied in Uppsala Sweden.

The increasing penetration of inverter based renewable generation in the form of solar photo-voltaic (PV) or wind has introduced numerous operational challenges and uncertainties. Among these challenges, one of the major ones is the impact on the transient stability of the grid. On the other hand, the direct methods for transient stability assessment of power systems have also fairly evolved over the past 30 years. These set of techniques inspired from the Lyapunov's direct method provide a clear insight into the system stability changes with a changing grid. The most attractive feature of these types of techniques is the heavy reduction in the computational burden by cutting down on the simulation time. These advancements were still aimed at analyzing the stability of a non-linear autonomous dynamical system and the existing power system perfectly fits that definition. Due to the changing renewable portfolio standards, the power system is undergoing serious structural and performance alterations. The whole idea of power system stability is changing and there is a major lack of work in the field of direct methods in keeping up with these changes. This dissertation aims at employing the pre-existing direct methods as well as developing new techniques to visualize and analyze the stability of a power system with an added subset of complexities introduced by PV generation. / Ph. D.

Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage operation has been proven to be very effective by several successful prototypes in recent years, there is no fast, effective, and comprehensive technique for designers to estimate power and delay of a design operating in the Ultra-Low-Voltage region. While some frameworks and mathematical models exist to estimate power or delay, certain limitations exist, such as being applicable to either power or delay, or within a certain region of transistor operation. This thesis presents a simulation framework that can quickly and accurately characterize a circuit from nominal voltage all the way down into the subthreshold region. The framework uses the nominal frequency and power of a target circuit, which can be obtained using gate-level or transistor-level simulation tools as well as normalized ring oscillator curves to predict delay and power characteristics at lower operating voltages. A specific contribution of this thesis is to introduce a weighted average method, which is a major improvement to a previously published form of this framework. Another contribution is that the amount of process variation in ULV regions of a circuit can be estimated using the proposed framework. The weighted averages framework takes into account the types of gates that are used in the circuit and critical path to give a more accurate power and timing characterization. Despite being many orders of magnitude lower than the nominal voltage, the errors are no greater than 11.27 percent for circuit delay, 16.96 percent for active energy, and 4.86 percent for leakage power for the weighted averages technique. This is in contrast to the original framework which has a maximum error of 39.75, 17.60, and 8.90 percent for circuit delay, active energy, and leakage power, respectively. To validate our framework, a detailed analysis is given in the presence of a variety of design parameters such as fanout, transistor widths, et cetera. In addition, we also validate our framework for a range of sequential benchmark circuits. / Master of Science

There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filter’s total harmonic distortion is less than –44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second.

There are growing industrial demands for low-voltage supply and low-power consumption circuits and systems. This is especially true for very high integration level and very large scale integrated (VLSI) mixed-signal chips and system-on-a-chip. It is mainly due to the limited power dissipation within a small area and the costs related to the packaging and thermal management. In this research work, two low-voltage, low-power integrated circuits used for data communication systems are introduced. The first one is a high performance continuous-time linear phase filter with automatic frequency tuning. The filter can be used in hard disk driver systems and wired communication systems such as 1000Base-T transceivers. A pseudo-differential operational transconductance amplifier (OTA) based on transistors operating in triode region is used to achieve a large linear signal swing with low-voltage supplies. A common-mode (CM) control circuit that combines common-mode feedback (CMFB), common-mode feedforward (CMFF), and adaptive-bias has been proposed. With a 2.3V single supply, the filter’s total harmonic distortion is less than –44dB for a 2VPP differential input, which is due to the well controlled CM behavior. The ratio of the root mean square value of the ac signal to the power supply voltage is around 31%, which is much better than previous realizations. The second integrated circuit includes two LVDS drivers used for high-speed point-to-point links. By removing the stacked switches used in the conventional structures, both LVDS drivers can operate with ultra low-voltage supplies. Although the Double Current Sources (DCS) LVDS driver draws twice minimum static current as required by the signal swing, it is quite simple and achieves very high speed operation. The Switchable Current Sources (SCS) LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to the previously reported LVDS drivers. Both LVDS drivers are compliant to the standards and operate at data rates up to gigabits-per-second.