Or, Pui Ying. / "July 2010." / Thesis (M.Phil.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references. / Abstracts in English and Chinese. / Acknowledgments / Table of Content / List of Figures / List of Tables / List of Publications / Chapter Chapter 1 - --- Background of LDO Research / Chapter 1.1 --- Structure of a LDO --- p.1-1 / Chapter 1.2 --- Principle of Operation of LDO --- p.1-2 / Chapter 1.3 --- Steady-State Specification of LDO --- p.1-3 / Chapter 1.4 --- High-Frequency Specification of LDO --- p.1-3 / Chapter 1.5 --- Dynamic Specification of LDO --- p.1-4 / Chapter 1.6 --- An Advanced LDO Structure --- p.1-4 / Chapter 1.7 --- Contribution and Outline of the Thesis --- p.1-5 / References --- p.1-6 / Chapter Chapter 2 - --- PSRR Analysis / Chapter 2.1 --- Modeling of the PSRR of LDO --- p.2-3 / Chapter 2.2 --- Analysis of LDO Circuit Using Proposed Modeling --- p.2-6 / Chapter 2.3 --- Conclusion of Chapter --- p.2-12 / References --- p.2-13 / Chapter Chapter 3- --- An Output-Capacitorless LDO with Direct Voltage-Spike Detection / Chapter 3.1 --- Analysis of Output-Capacitorless LDO --- p.3-5 / Chapter 3.2 --- LDO with Proposed Voltage-Spike Detection Circuit --- p.3-7 / Chapter 3.3 --- Experimental Results --- p.3-15 / Chapter 3.4 --- Conclusion of Chapter --- p.3-21 / References --- p.3-22 / Chapter Chapter 4 - --- A LDO with Impedance Adjustment and Loop-Gain Boosting Technique / Chapter 4.1 --- Proposed LDO --- p.4-3 / Chapter 4.2 --- Experimental Results --- p.4-7 / Chapter 4.3 --- Comparison --- p.4-11 / Chapter 4.4 --- Conclusion of Chapter --- p.4-12 / Reference --- p.4-13 / Chapter Chapter 5 - --- Conclusion and Future Work

The following dissertation addresses a novel low cost process developed to fabricate a Vertical Organic Field Effect Transistor (VOFET). The solution processable VOFET is designed, fabricated and tested in the context of bioengineering domains. The scope of distinct biomedical applications has also been explored. Organic thin-film transistors are gathering industrial attention as a potential candidate for future electronics analogous to silicon technology. Low fabrication cost, structural miniaturization and low operational voltage are the challenges for fabricating an Organic Field Effect Transistor (OFET). To create these devices, OFETs require new design paradigms and wet processing routes. However, conventional lateral OFET geometry cannot satisfy these demands because of process complexities and the high cost to achieve sub-micron channel length. Despite these barriers, solvent sensitivity towards organic semiconductors, electrode patterning and masking make this process more challenging than are associated with current technologies. Therefore, the need for production of a low cost high efficiency OFET is of high importance. The soluble organic semiconductor exhibits promising device properties. The growing demand of organic electronics poses great difficulty in adapting standard photolithography patterning for fabrication. The main issue is incompatibility in handling organic materials. To circumvent these challenges, a novel fabrication process has been developed to build OFETs in vertical geometry. The novelty of this process allows for creation of sub-micron channel devices at very low cost. Solution processed VOFET devices are fabricated using a 13,6-N-sulfinylacetamidopentacene (NSFAAP) precursor. Low cost fabrication techniques such as spin coating and drop casting are employed for achieving submicron channel length. Nanoscale devices, i.e. channel lengths, L=265nm, 300nm and 535nm, are respectively fabricated using the spin coating technique. Output characteristics are recorded at an operational voltage of 1volt. Short channel effects dominate the device performance, resulting in a linearity effect in I-V characteristics. Strategies, such as perforated source electrode design and drop casting techniques, are evolved and employed to minimize the short channel effects. Space Charge Limited Current (SCLC) effects, better known as short channel effects, are observed during I-V characterizations at high longitudinal fields. The drop casting technique is used over Patterned Electrode (PE) for reducing these SCLC effects. Thick channel devices, i.e. L=2µm, are fabricated to minimize the SCLC effects. Low cost polyimide 3M kapton tape is used as masking material in between the stacked layers. Time-temperature balance is optimized during the precursor to pentacene growth process. Metrological characterizations such as TEM, SEM, AFM, Raman Spectroscopy and X-RD are performed to confirm the precursor to pentacene conversion. AFM scanning illustrates dendritic pentacene molecular growth at 170°C annealing. Consequently, the conversion temperature is optimized around 200°C. In life sciences, there is always striving for translational technology development that can mimic, integrate and manipulate the biological system. Electrical signals enhance the capabilities of electronics to interact and understand the signaling pathways in a biological system. Keeping this in view, the potential applications into biomedical areas, such as flexible sensors and biomedical imagers, are proposed. VOFET has been proposed as a mainstay for flexible cardiac sensors and as imagers. OFET sensors could be designed to cover highly stretchy and arbitrary cardiac tissue. Sensor web integration with pacemakers and Implantable Cardioverter Defibrillator (ICD) device systems has been proposed. The OFET imaging sensor holds potential for early detection of cancer by detecting nuclear level changes in breast cancer images. Nuclear pleomorphic (shape and size distortion of cancerous nuclei) feature detection and analysis could be a step forward in the direction of digital pathology. The conventional analysis approach is time-consuming and error prone as it depends on visual inspection by pathologists. The proposed approach is parallel in nature and supports the existing method of cancer detection.

<p>Due to rapid growth of home entertainment consumer market, video technology has been continuously pushed to deliver sharper pictures with higher resolution. This has brought about stringent requirements on the video analog front end, which often coupled with the low power and low voltage regulations had to deal with short channel effects of the deep submicron CMOS processes.</p><p>This thesis presents the design of a fully differential programmable gain amplifier, as a subcircuit of a larger video digitizing IC designed at division of Electronic Systems. The switched capacitor architecture of the PGA does not only buffer the signal, but performs compensation for the sync-tip of analog video signal.</p><p>The pseudo differential OTA eliminates tail current source and maintains high signal swing and has efficient common mode feedforward mechanism. When coupled with a similar stage provides inherent common moode feedback without using an additional SC-CMFB block.</p><p>The PGA has been implemented using a 65 nm digital CMOS process. Expected difficulties in a 1.2 V OTA design make themselves evident in 65 nm, which is why cascaded OTA structures were inevitable for attaining gain specification of 60 dB. Nested Miller compensation with a pole shifting source follower, stabilizes the multipole system. The final circuit attains up to 200 MHz bandwidth and maintains high output swing of 0.85 V. High slew rate and good common mode and power supply rejection are observed. Noise requirements require careful design of input differential stage. Although output source follower stabilized the system, it reduces significant bandwidth and adds to second order non-linearity.</p>

A method for improving performance/watt of an embedded single-instruction multiple-data (SIMD) architecture using application-guided a priori scheduling of hardware resources is presented. A multi-core architectural simulator is adopted that accurately estimates power, performance, and utilization of various processor components (logic, interconnect and memory). A greedy search is then performed on each algorithm block of a signal processing chain in order to schedule each component's throughput and power. The proposed software-directed hardware rebalancing, applied to a typical electroencephalography (EEG) filtering chain, is analyzed for two different SIMD architectures. The first, representing a super V[subscript th] processor demonstrates a 51%-86% improvement in performance/watt at 1%-10% throughput reduction using block level or algorithm level a priori scheduling. The second architecture used is Synctium, a near V[subscript th] processor which demonstrates 50%-99% performance/watt improvement across the same throughput reduction range and optimization techniques. / Graduation date: 2012

Power and timing requirements are becoming more and more stringent as applications move from less mobile devices to more mobile ones. As such, it is important to optimize these applications as much as possible in order to provide the best solution that is low power and low latency. Although there are many different techniques to achieve a low power, low latency solution, this thesis focuses specifically on low power scheduling at the behavioral level where resource-constrained scheduling is the technique of choice since it directly considers the resource limitations of mobile devices. Conventional resource-constrained scheduling schemes are concerned with minimizing the latency or improving the speed of an algorithm--represented by a data flow graph (DFG)--given a limitation on resources. However, these conventional resource-constrained scheduling schemes are no longer applicable since power has grown to be a major issue, especially in mobile devices. Hence, the conventional resource-constrained scheduling schemes gave way to current resource-constrained scheduling schemes that utilize multiple voltages, which work to find a balance between speed and power. These current multiple voltage schemes use various techniques to balance and meet the speed and power requirements. But while they do a good job of meeting these requirements, they fail to address a new issue that is beginning to surface the number of memory registers needed. Therefore, to address this new arising issue, this paper presents a novel resource-constrained scheduling scheme that balances the speed, power, and register requirements. This algorithm is compared to both a conventional resource-constrained scheduling scheme and a current resource-constrained scheduling scheme with multiple voltages to show that it performs better in finding a scheduling solution. Benchmark results show that, on average, our algorithm has a better power savings while keeping the maximum number of registers needed and the latency low compared to conventional resource-constrained scheduling schemes and current resource-constrained scheduling schemes utilizing just multiple voltages. / Graduation date: 2004

Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low-voltage conditions. There are several well-known techniques to bypass the problem. These approaches include: (1) The clock boosting schemes (e.g. 2VDD clock signal) which cannot be used in submicron low-voltage CMOS processes as gate oxide can only tolerate the technology's maximum voltage (VDD). (2) The use of scaled/lower threshold transistors, which are not always scalable to very low voltage supplies as it could suffer from an unacceptable amount of leakage current (e.g. the switch may not be fully turned off). (3) The use of bootstrapped clocking, which has added loading and possible reliability issues. (4) The switched-opamp (SO) technique which is fully compatible with low-voltage submicron CMOS processes but the operating speed limited due to slow transients from the opamp being switched off and on. In this thesis, the Opamp-Reset Switching Technique (ORST) topology is proposed for low-voltage operation. Instead of opamps being turned on and off as in the switched-opamp technique, the sourcing amplifier is placed in the unity-gain reset configuration to provide reset level at the output. In this way, high-speed operation is possible. The technique is applied to two ADCs as examples of low-voltage design. The first design is a 10-bit 25MSPS pipelined ADC using pseudo-differential structure. It is fabricated in a 0.35-��m CMOS process. It operates at 1.4V and consumes 21mW of total power. The second design is a two-stage algorithmic ADC with highly linear input sampling circuit. In addition to the low-voltage design techniques used in the pipelined ADC, radix-based digital calibration technique for multi-stage ADC is also proposed. The ADC uses a 0.18-��m CMOS technology. It operates at 0.9V supply with total power consumption of 9mW. Experimental results show that the proposed calibration technique reduces spurious free dynamic range from 47dB to 75dB and improves signal-to-noise and distortion ratio from 40dB to 55dB after calibration. / Graduation date: 2003

Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor (SC) circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low voltage conditions. There exist three techniques to solve the problem, but with their own limitations. Multi-threshold process increases cost. Boosted clock will cause life time reliability issues. Switched-opamp slows down the speed of operation. A new low-voltage SC technique without special process and boosted-clock is studied to overcome these drawbacks. To verify the speed advantage of the new scheme over the switched-opamp technique, a 10-bit 20 MS/s pipeline A/D converter operating at 1.5 V supply voltage was designed. A new pseudo-differential structure was proposed and some relevant design issues are discussed. Circuit implementations and layout floorplan are described. All designs are based on Matlab, SWITCAP and Hspice simulation. / Graduation date: 2000

Power optimization becomes more and more important due to the design cost and reliability. Sometimes high power consumption means expensive package cost and low reliability. The first step in optimizing power consumption is determining where power is consumed within a processor. While system-level code tracing and bit transition calculation are not enough to estimate the power distribution, transistor-level HSPICE simulation to model a microprocessor is too complex and time-consuming. In our research, a VHDL model with enhanced signal tracing function will be developed based on the existing VHDL behavior model. The power consumption of superscalar microprocessor in terms of switching activity and capacitance will be carefully studied. Two factors served as the basis for study: accessibility and importance for power calculations. A brief examination of the datapath suggests that the register file, the instruction cache and data cache are some of the major contributors to power usage. It was therefore decided to track the input and output bit transitions to these modules. These transitions are counted along with the number of accesses to each of the modules. In order to gather all of this data, the original VHDL model simulator has been enhanced. As instructions pass through the CPU, additional code is required to track and record the necessary information. For each individual instruction in the ISA, various information is recorded based on the elements in the processor that the instruction affects. For instance, if the simulator is about to execute a load instruction, the instruction uses the programmer counter, the instruction bus, data bus, the address bus, the ALU (adder) and the register file. The information being recorded for each of these elements must be updated to reflect the execution of that particular load instruction. Also, the inside circuit of each module, i.e. register file, instruction cache and data cache and the 6-transistor memory cell layout considering the 0.25��m CMOS technology will be studied in order to extract the capacitance. We do not need very accurate, absolute power estimation, therefore, we will try to keep the model simple. / Graduation date: 2000

The major limiting factor of DRAM access time is the low transconductance of the MOSFET's which have only limited current drive capability. The bipolar junction transistor(BJT) has a collector current amplification factor, ��, times base current and is limited mostly by the willingness to supply this base current. This collector current is much larger than the MOSFET drain current under similar conditions. The requirements for low power and low power densities results in lower power supply voltages which are also inconsistent with the threshold voltage variations in CMOS technology, as a consequence at least pulsed body bias or synchronous body bias will probably be utilized. Given that of the CMOS body will be driven or the CMOS gate and body connected a BJT technique is proposed for ultra low voltages like Vdd=0.5. Utilizing present CMOS process technology good results can be achieved with ultra low power using gate-body connected transistors and a current sense amplifier. / Graduation date: 1999

In recent years, the rapidly growth of CMOS technology has evolved towards submicron and deep-submicron features. Due to smaller device sizes, and significant demand for low-power designs, the maximum allowable power supply voltage is restricted. So far, two solutions; clock boosting and switched opamp schemes have been proposed. The material presented in this thesis shows the drawback of these schemes while presenting three new methods for realizing low-voltage switched-capacitor integrators which are the key stages of ����� modulators and SC filters. Using these integrators, several circuit realizations of SC filters and second order ����� modulators will be shown. / Graduation date: 1999