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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
11

Design and Analysis of a Multi-Processor Communication Protocol for Real Time Sensor Data

Franke, Markus. Baumgartl, Robert. January 2008 (has links)
Chemnitz, Techn. Univ., Diplomarb., 2008.
12

Effiziente Nutzung der Finite-Element-Methode auf Mehrprozessorrechnern /

Lengen, Hinderk van. Van Lengen, Hinderk. January 1900 (has links)
Thesis--Universitat-Gesamthochschule Paderborn, 1996.
13

Verfahren zur schnellen Lösung von grossen Gleichungssystemen in der Momentenmethode

Astner, Miguel January 2009 (has links)
Zugl.: Hamburg, Techn. Univ., Diss., 2009
14

A formal fault model for component based models of embedded systems

Fischer, Marco January 2006 (has links)
Zugl.: Chemnitz, Techn. Univ., Diss., 2006
15

Predicting software performance in symmetric multi-core and multiprocessor environments

Happe, Jens January 2008 (has links)
Zugl.: Oldenburg, Univ., Diss., 2008 / Hergestellt on demand
16

Performance of sequential batching based methods of output data analysis in distributed steady state stochastic simulation

Souza Mota, Edjair de. Unknown Date (has links) (PDF)
Techn. University, Diss., 2002--Berlin.
17

Design and Analysis of a Multi-Processor Communication Protocol for Real Time Sensor Data

Franke, Markus 23 September 2008 (has links) (PDF)
At IAV GmbH, Chemnitz, an embedded platform for high-performance sensor data acquisition has been developed. Sensor data is gathered and preprocessed by two digital signal processors (DSP) which communicate bidirectionally via dual-ported memory with the central controlling instance, a Freescale MCF5484 microcontroller running uClinux. The goal of this thesis is to design, implement, analyze and optimize a real-time communication protocol between both DSPs and the microcontroller. The challenges of this thesis can be defined as follows: • A uClinux driver for the dual-ported RAM must be implemented. This driver has to employ the microcontroller’s internal DMA engine and should be integrated into the Linux kernel’s DMA framework. • The DMA engine must be thoroughly analyzed. Especially interesting is its behavior when concurrently performing data transfers. Potential influence factors onto data transfer performance and timing predictability should be experimentally identified and quantitatively characterized, if possible. • Sensor data from the DSPs to the microcontroller has to meet real-time demands and must be prioritized in some way over status and parameter data from and to the DSPs. • Correct and efficient synchronization is a must. If possible, different synchronization schemes should be compared to each other. • The achievable performance in terms of guaranteed and maximum data throughput between DSP and microcontroller as well as end-to-end bandwidth has to be estimated. • Apart from the DMA engine analysis, a general evaluation of potential and achieved performance, timing predictability and the remaining microcontroller’s processing capacity (if any) should be executed.
18

Dynamically reconfigurable dataflow architecture for high performance digital signal processing on multi FPGA platforms

Voigt, Sven-Ole January 2008 (has links)
Zugl.: Hamburg, Techn. Univ., Diss., 2008
19

On the modeling and evaluation of real-time systems /

Naedele, Martin. January 2000 (has links)
Diss. no. 13564 techn. sc. SFIT Zurich. / Im Buchh.: Aachen : Shaker. Literaturverz.
20

Schedulability Tests for Real-Time Uni- and Multiprocessor Systems / Planbarkeitstests für Ein- und Mehrprozessor-Echtzeitsysteme unter besonderer Berücksichtigung des partitionierten Ansatzes

Müller, Dirk 07 April 2014 (has links) (PDF)
This work makes significant contributions in the field of sufficient schedulability tests for rate-monotonic scheduling (RMS) and their application to partitioned RMS. Goal is the maximization of possible utilization in worst or average case under a given number of processors. This scenario is more realistic than the dual case of minimizing the number of necessary processors for a given task set since the hardware is normally fixed. Sufficient schedulability tests are useful for quick estimates of task set schedulability in automatic system-synthesis tools and in online scheduling where exact schedulability tests are too slow. Especially, the approach of Accelerated Simply Periodic Task Sets (ASPTSs) and the concept of circular period similarity are cornerstones of improvements in the success ratio of such schedulability tests. To the best of the author's knowledge, this is the first application of circular statistics in real-time scheduling. Finally, the thesis discusses the use of sharp total utilization thresholds for partitioned EDF. A constant-time admission control is enabled with a controlled residual risk. / Diese Arbeit liefert entscheidende Beiträge im Bereich der hinreichenden Planbarkeitstests für ratenmonotones Scheduling (RMS) und deren Anwendung auf partitioniertes RMS. Ziel ist die Maximierung der möglichen Last im Worst Case und im Average Case bei einer gegebenen Zahl von Prozessoren. Dieses Szenario ist realistischer als der duale Fall der Minimierung der Anzahl der notwendigen Prozessoren für eine gegebene Taskmenge, da die Hardware normalerweise fixiert ist. Hinreichende Planbarkeitstests sind für schnelle Schätzungen der Planbarkeit von Taskmengen in automatischen Werkzeugen zur Systemsynthese und im Online-Scheduling sinnvoll, wo exakte Einplanungstests zu langsam sind. Insbesondere der Ansatz der beschleunigten einfach-periodischen Taskmengen und das Konzept der zirkulären Periodenähnlichkeit sind Eckpfeiler für Verbesserungen in der Erfolgsrate solcher Einplanungstests. Nach bestem Wissen ist das die erste Anwendung zirkulärer Statistik im Echtzeit-Scheduling. Schließlich diskutiert die Arbeit plötzliche Phasenübergänge der Gesamtlast für partitioniertes EDF. Eine Zugangskontrolle konstanter Zeitkomplexität mit einem kontrollierten Restrisiko wird ermöglicht.

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