Graduation date: 1996

The semiconductor gallium arsenide (GaAs) has many potential advantages over the more widely used semiconductor silicon (Si). These include higher low field mobility, semi-insulating substrates, a direct band-gap, and greater radiation hardness. All these advantages offer distinct opportunities for implementation of new circuit functions or extension of the operating conditions of similar circuits in silicon based technology. However, full exploitation of these advantages has not been realized. This study examines the limitations imposed on conventional GaAs metal-semiconductor field effect transistor (MESFET) technology by deviations of the semi-insulating substrate material from ideal behavior. The interaction of the active device with defects in the semi-insulating GaAs substrate is examined and the resulting deviations in MESFET performance from ideal behavior are analyzed. A p-well MESFET technology is successfully implemented which acts to shield the active device from defects in the substrate. Improvements in the operating characteristics include elimination of drain current transients with long time constants, elimination of the frequency dependence of g[subscript ds] at low frequencies, and the elimination of sidegating. These results demonstrate that control of the channel to substrate junction results in a dramatic improvement in the functionality of the GaAs MESFET. The p-well MESFET RF characteristics are examined for different p-well doping levels. Performance comparable with the conventional GaAs MESFET technology is demonstrated. Results indicate that optimization of the p-well MESFET doping levels will result in devices with uniform characteristics from DC to the highest operating frequency. / Graduation date: 1991

A complete Gallium Arsenide Metal Semiconconductor Field Effect Transistor (GaAs MESFET) model including deep-level trap effects has been developed, which is far more accurate than previous equivalent circuit models, for high-speed applications in linear integrated circuit design. A new self-backgating GaAs MESFET model, which can simulate low frequency anomalies, is presented by including deep-level trap effects which cause transconductance reduction and the output conductance and the saturation drain current to increase with the applied signal frequency. This model has been incorporated into PSPICE and includes a time dependent I-V curve model, a capacitance model, a subthreshold current model, an RC network describing the effective substrate-induced capacitance and resistance, and a switching resistance providing device symmetry. An analytical approach is used to derive capacitances which depend on Vgs and Vds and is one which also includes the channel/substrate junction modulation by the self backgating effect. A subthreshold current model is analytically derived by the mobile charge density from the parabolic potential distribution in the cut-off region. Sparameter errors between previous models and measured data in conventional GaAs MESFET's have been reduced by including a transit time delay in the transconductances, gm and gds, by the second order Bessel polynomial approximation. As a convenient extraction method, a new circuit configuration is also proposed for extracting simulated S-parameters which accurately predict measured data. Also, a large-signal GaAs MESFET model for performing nonlinear microwave circuit simulations is described. As a linear IC design vehicle for demonstrating the utility of the model, a 3-stage GaAs operational amplifier has been designed and also has been fabricated with results of a 35 dB open-loop gain at high frequencies and a 4 GHz gain bandwidth product by a conventional half micron MESFET technology. Using this new model, the low frequency anomalies of the GaAs amplifier such as a gain roll-off, a phase notch, and an output current lag are more accurately predicted than with any other previous model. This new self-backgating GaAs MESFET model, which provides accurate voltage dependent capacitances, frequency dependent output conductance, and transit time delay dependent transconductances, can be used to simulate low frequency effects in GaAs linear integrated circuit design. / Graduation date: 1991

Thesis (M.E.)--University of Canterbury, 2009. / Typescript (photocopy). "November 2009." Includes bibliographical references (leaves 73-78). Also available via the World Wide Web.

Thesis (M.S.)--Rochester Institute of Technology, 2006. / Typescript. Includes bibliographical references.

The object of the work described in this thesis was to develop GaAs integrated circuit modeling techniques based on a modified version of SPICE 2, then layout, fabricate, model and test ion implanted GaAs MESFET integrated sample and hold circuits. A large signal GaAs MESFET model was used in SPICE to evaluate the relative performance of inverted common drain logic (ICDL) digital integrated circuits compared to other circuit configurations. The integrated sample and hold subsequently referred to as an integrated sampling amplifier block(ISAB), uses a MESFET switch with either one or two guard gates to suppress strobe feedthrough. Performance guidelines suggested by the project sponsor indicate an optimal switch sampling pulse width capability of 25 ps with 5 ps rise and fall time. Guard gates are included in the switch layout to evaluate pulse feedthrough minimization. The project sponsor suggested -20 dB pulse feedthrough isolation and minimum sampling switch off isolation of -20 dB at 10 GHz as project guidelines. Simulations indicate that a 0.5 µm gate length process approaches the suggested performance guidelines. A mask layout was designed and modeled including both selective implant and refractory self aligned gate processes. The refractory self aligned gate process plasma etched t-gate structure produces a sub 0.5 µm gate length. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

The conversion gain of GaAs MESFET mixers is known to be dependent on the impedances seen by the applied signals and the resulting mixing products at all ports of the device. For an accurate representation, all these loading conditions should be considered; however, the design of gate and drain networks then becomes rather difficult. As a result, no sufficiently accurate and yet usable design procedures exist for MESFET mixers; instead, a few simple rules involving short- and open-circuit terminations have been given by various authors. Unfortunately, these rules are often inappropriate, particularly in upconverter applications. In this thesis, the conversion efficiency dependence on the drain loading at the local oscillator frequency has been studied for a gate upconverter; the local oscillator signal is by far the most dominant in terms of its influence on mixer performance. It has been found that the conversion gain can significantly deteriorate for a narrow range of load values. In addition, the local oscillator drain termination resulting in highest gain has been found to be generally different from the short-circuit recommended in the literature. Based on these findings, a novel FET upconverter design procedure has been developed that incorporates the local oscillator loading phenomenon in the FET equivalent circuit by means of a load dependent mixing transconductance. It allows the optimization of the drain network for an acceptable match at the selected sideband and desired local oscillator rejection while avoiding impedance values in the local oscillator frequency range which would otherwise cause severe degradation in conversion gain. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

For VLSI applications, it is essential to have consistent device characteristics for devices fabricated on different fabrication runs, on different wafers, and especially across a single wafer. MESFETs fabricated on GaAs have been found to have an orientation dependence in their threshold voltage and other characteristics. For MESFETs with gate length less than 2 μm, changing the device orientation can so significantly alter the device characteristics that it must be considered during the transistor design stage. The causes for the orientation dependence in the device characteristics have been suggested to be the piezoelectric property of GaAs and stress in the substrate. Stress produced by the encapsulating dielectric film generates a polarization charge density in the substrate. If the magnitude of the polarization charge density is large enough to alter the channel doping profile, then the device characteristics are changed. In this thesis, the effects of stress on GaAs MESFET device characteristics were studied by modelling and experimental works. In the modelling part, polarization charge densities under the gate of an encapsulated MESFET were calculated by using the so called distributed force model and the edge concentrated model. The distributed force model is a much better model because it describes more realistically the stress distribution in the film and in the substrate. It should provide a much more accurate calculation of the induced polarization charge density. The results show that the polarizarition charge densities calculated by the two models have similar distribution pattern, but the magnitudes are very different. With an identical set of conditions, a much larger polarization charge density is predicted by the edge concentrated model. In addition, the distributed force model distinguishes different films by a "hardness" value, based on their elastic property, whereas the edge concentrated model does not. A film with a larger "hardness" value is predicted to generate a larger polarization charge density. Two types of film were considered, SiO₂ and Si₃N₄. Using bulk film characteristics, the calculations showed that Si0₂ film is "harder" than Si₃N₄ film. If an equal built-in stress value is assumed, then a larger polarization charge density is predicted for Si0₂ than for Si₃N₄ encapsulated substrates. In the experimental part, stress was applied to test devices by bending strips of GaAs wafers in a cantilever configuration. MESFETs tested were oriented in the [011] or the [011̅] direction. Both static stress and time-varying stress were applied. In the statics stress experiment, the changes in the barrier height and the C-V profile were measured. It was found that, with equal stress applied, Schottky barriers with a larger ideality factor showed a larger change in the barrier height. In the time-varying stress experiment, attempts were made to measure the effect of the polarization charge density on device characteristics by measuring changes in the drain-source current. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

<p>An <em>isotype heterojunction</em> is a junction between two layers of dissimilar semiconductors both of which are doped either n-type or p-type. These semiconductor structures are found in a variety of optoelectronic devices, such as solar cells, semiconductor lasers, and detectors. Motivated by the structure of third generation inorganic solar cells, this thesis concentrates on the analytical modelling of isotype heterojunctions and its application to the design optimization of these devices. The main development of this work is the introduction of an analytical expression for the current density across an isotype heterojunction valid for arbitrary doping concentration ratios. This result generalizes the standard expression found in the literature, which is limited by the assumption that the doping concentration ratio between the two sides of the heterojunction is equal to one. The generalization is developed by employing the Lambert W function in the solution of the electrostatic boundary condition associated with the heterojunction interface. As done in the derivation of the standard expression found in the literature, the generalization only considers thermionic emission, but the same method can readily be applied for other transport mechanisms. A key feature of this generalized result is that it mathematically contains the expression for the current density across a metal-semiconductor Schottky contact as a limiting case, thereby unifying the treatment of these two heterointerfaces into a single general analytical description. This latter find is particularly significant from a theoretical perspective, considering that the two heterointerfaces are traditionally described as separate topics in the presentation of semiconductor device theory.</p> / Master of Applied Science (MASc)

Metal-semiconductor-metal (MSM) photodetectors are becoming attractive devices for optoelectronic integrated circuits due to their high speed and simplicity. Optoelectronic matrix switches based on MSM detector arrays offer many advantages such as zero-bias off-state, low bias voltage, high speed and large bandwidth. While in many applications the optical input is coupled in through the top surface of the device, optical signals can also be distributed through transparent waveguides that are located below the absorbing detector layer. Such waveguide-coupled detectors will act as optical taps when the coupling between the waveguide and detector layers is well under control. In this thesis, a 4x4 MSM waveguide-coupled optoelectronic matrix switch was demonstrated and analyzed. The strength of the coupling between the waveguide and detector layers was predicted theoretically and confirmed experimentally. Franz-Keldysh effect in this device was also demonstrated. / Thesis / Master of Engineering (ME)