Thesis (M.S.)--Rochester Institute of Technology, 1988. / Typescript. Includes bibliographical references (leaves 172-173).

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International Telemetering Conference Proceedings / October 17-20, 1988 / Riviera Hotel, Las Vegas, Nevada / The Goddard Space Flight Center Mission Operations and Data Systems Directorate has developed a Packet Processor card utilizing semi-custom very large scale integration (VLSI) devices, microprocessors, and programmable gate arrays to support the implementation of multi-channel telemetry data capture systems. This card will receive synchronized error corrected telemetry transfer frames and output annotated application packets derived from this data. An adaptable format capability is provided by the programmability of three microprocessors while the throughput capability of the Packet Processor is achieved by a data pipeline consisting of two separate RAM systems controlled by specially designed semi-custom VLSI logic.

All of the communication, IA, and the cellular phone need the capabilities which can be provided by the ARM microprocessor that has the advantages with high efficient, low power consumption, and low cost. According to the market research that Gartner proposed, ARM occupied the highest with 54% at the market of embedded microprocessor, and 70% of the cellular phones utilize the ARM kernel techniques in the whole world. The success of ARM is determined by the different on the hardware design compared with the general embedded microprocessor. In my thesis, the significant propose is to study the practicability and the essentiality of the hardware characters of the ARM microprocessor applied on different products. We design ¡§automatic register backup/restore system¡¨ to replace ARM¡¦s banked registers. This design is capable of reducing the circuit area of the register file by 27.6% and reducing the read delay of register file by 18.4%. We use a simpler method (TAP instruction) to select scan-chain for test mechanism.

The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique which features many advantages, such as low demand for hardware and repeatable use of the pins on the JTAG port. The development of system-on-chip technology has matured significantly in recent years. The microprocessors in system-on-chip designs have been applied in a variety of ways, and different microprocessors are being used in the embedded system. The traditional modus operandi of debug control, in which an ad hoc hardware/software package is required for each microprocessor, is not economical as far as programming and designing are concerned. Thus it is advisable to design a more flexible debug control hardware/software package which can fit into different embedded microprocessors with in-circuit emulators. This thesis reviews several types of embedded in-circuit emulator structure and comes up with a parameterized, modularized hardware/software package for controlling in-circuit emulators. An initial analysis of microprocessor systems and embedded debug circuits helps us to elicit reusable parameters so that we can achieve our desired debug control by simply adjusting parameters when we work on different microprocessor architectures and embedded debug circuits. An ensuing examination of the reusability and functionality of our designed debug control hardware/software enables us to group all the functions of our hardware/software package into different functional modules so that we can simply replace relevant functional modules on different microprocessor architectures and embedded debug circuits. The parameterized design allows us to use a single debug control software program on different microprocessor systems with the slightest change of parameter setting. The modularized model has the merit of minimizing our effort of debug control through module replacement when we need to adapt our software to a new environment (as when we want to use it on a different operating system or when we want to apply it to a different communication interface).

ARM microprocessor is one of the CPU most extensively applied to electronic products in the market, with the advantages of high efficiency, low power consumption, and low cost. The purpose of this thesis is to design and implement an ARM10-like microprocessor SYS32TME-III, it is based on the frame of 32-bits RISC architecture of ARM10, and to analyze the character of derivative architecture on RTL design with the point of view between the process of the design and implementation. For design strategy, speed 200MHz is the goal, and performance-optimized is the main point. Then, improve the mechanisms of adopting instruction pre-fetch, branch prediction, parallel execution, executive path of instruction and operation unit, and compare its results, probe into what¡¦s learning from the design.

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Thesis (M.S.)--Ohio University, November, 1983. / Title from PDF t.p.

The ultimate goal of Computer-Aided Design research in the area of digital circuits is the automatic synthesis of a complete solution from a behavioural specification. This thesis describes an attempt to attain this ideal in the more limited realm of designing single-board control systems, constructed from general-purpose microprocessor components. The difficulties currently encountered in designing and implementing microprocessor control systems are outlined, and the architecture of an integrated, knowledge-based design system is proposed as a method of overcoming these difficulties. The design system encompasses both behavioural and structural design functions. However, only the tools and techniques required to fulfil the behavioural design functions are considered in detail in this project. A review of previous work in the field of automated digital circuit design and software and hardware specification languages is presented. The major features of a novel language for specifying and simulating control system behaviour are then described, together with an intermediate design description notation, which facilitates the generation of microprocessor assembly language code directly from behavioural specifications. The design and implementation of a fast, generalised microprocessor simulation facility constructed from transputers is discussed, and its performance potential analysed. The simulation facility enables the complete design for a given application to be tested, before any actual hardware construction takes place. Finally, an evaluation of the behavioural specification, synthesis and simulation techniques developed in this project is presented, and the benefits perceived from adopting such techniques are summarised. Issues concerning the integration of these techniques with the knowledge-based structural design tools are also dealt with, and suggestions for further developments and enhancements are identified.

Thesis deals with support of educational courses focused to single chip microprocessors in secondary schools. It includes a text introducing students to the use of single microprocessor and provides examples to their applications.