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As electronic packages and their thermal solutions become more complex the reliability margins in the thermal solutions diminish and become less tolerant to errors in reliability predictions. The current method of thermally stress testing thermal solutions can be over or under predicting end of life thermal performance. Benefits of accurate testing and modeling are improved silicon yield in manufacturing, improved performance, lower cost thermal solutions, and shortened test times. The current method of thermally stress testing is to place the entire unit in an elevated isothermal temperature and periodically measure thermal performance. Isothermally aging is not an accurate representation of how the unit will be used by the customer and does not capture the thermal gradients and mechanical stresses due to different coefficients of thermal expansion of the materials used in the thermal solution. A new testing system, CITRAM which is an acronym for Constant Interface Temperature Reliability Method, has been developed that uses an electronic test board. The approach captures the thermal and mechanical stresses accurately and improves test time by 20-30% as a result of automation. Through this study a difference in the two methods has been identified and the new CITRAM method should be adopted as current practice.

ABSTRACT Many aspects of speculative multithreading have been under constant and crucial research in the recent times with the increased importance in exploiting parallelism in single thread applications. One of the important architectural optimizations that is very pertinent in this scenario is branch prediction. Branch Prediction assumes increased importance for multi-threading systems that execute threads speculatively, since wrong predictions can be much costlier here, in terms of threads, than a few instructions that occupy the pipeline in a uni-processor. Conventional branch prediction techniques have provided increasingly better prediction accuracies for uni-core processing. But the branch prediction itself takes on a whole new dimension when applied to multi-core architectures based on Speculative Multithreading. Dependence on global branch history has helped branch predictors to achieve high prediction accuracy in single thread applications. The discontinuity of global history created at the thread boundaries cripple the performance of branch predictors in a multi-threaded environment. Many studies in the past have tried to address the branch history problem to improve the prediction accuracy. Most of these have been found either to be architecture specific or complex in terms of the hardware needed to recreate or approximate the right history to be given to the threads when they start executing out of order. This hardware overhead increases as the number and size of threads increase thereby limiting the scalability of the algorithms proposed so far. The current thesis takes a different direction and proposes a simple and scalable solution to effectively reduce the misprediction rates in Speculative Multithreaded systems. This is accomplished by making use of a synergistic interaction between threads to boost the inherent biased nature of branches and using less complex hardware to reduce aliasing between branches in the threads. The study proposes a new scheme called the Global Broadcast Buffer scheme to effectively reduce branch mispredictions in Speculative Multithreaded architectures.

Thesis. 1976. M.S.--Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. / Microfiche copy available in Archives and Engineering. / Bibliography: leaves 165-167. / M.S.

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Analyses and designs of a peak-power tracking system using microprocessor control are performed. Large-signal stability of the system for various modes of operation is analyzed to predict system dynamics. The stability analysis is supported mainly by qualitative graphical representations of different component blocks of the system. Small-signal stability analysis around the equilibrium points is done to assure proper performance and operation of this particular peak-power tracking system. Specific design details and procedures are discussed, and predictions from the analyses are verified through hardware. / Master of Science

M. S.

In many applications the microprocessor can represent an attractive design alternative to hardwired integrated circuitry. Such designs can offer substantial in teras of flexibility, cost and reliability, generally at the expense of operating speed. This paper contains a detailed description of such a system, in which a Zilog Z80 microprocessor is used as the basis for an intelligent controlling interface between an assortment of experimental instruments and a PDP-11 minicomputer. The details of the hardware and software designs, which could be employed in a wide range of experiment and process control applications, are presented. / M. S.

Typescript (photocopy). / Digitized by Kansas State University Libraries / Department: Electrical and Computer Engineering.