Spelling suggestions: "subject:"microprocessor""
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Microprocessor control system for the injection molding processHaber, Andrew. January 1982 (has links)
No description available.
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Multilevel interconnect architectures for gigascale integration (GSI)Venkatesan, Raguraman 05 1900 (has links)
No description available.
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Protocolos en redes de microcontroladoresLópez, Ricardo A. January 2010 (has links)
Los microcontroladores están inmersos en nuestra forma de vida. Los encontramos en automóviles, lavarropas, celulares, reproductores MP3, agendas y en un sinfín de sitios en nuestra vida cotidiana. La capacidad de integración a muy alta escala (VLSI) -con crecimiento casi exponencial en los últimos años-, hace que estos dispositivos cada día contengan más y más funciones que antes eran impensadas. Debido a ello, una agrupación de estos dispositivos conectados en red, configura un sistema de control muy poderoso, que dotado de algún protocolo normalizado que permita su interconexión a Internet, le da un alcance prácticamente ilimitado y de gran escalabilidad. Por lo expuesto, en esta tesis se estudiará la implementación de una red de microcontroladores, definiendo funciones de Control y adquisición de datos, equivalentes a los sistemas de Control y Adquisición de Datos (SCADA) de gran escala. Sobre la definición efectuada, surgirá un protocolo de aplicación que permitirá así un desarrollo Top-Down del sistema. Sobre la base de la definición lograda, este primer capítulo describe en un modo general los alcances de la tesis, donde se estudiarán entre otros aspectos, los protocolos de capas de comunicaciones para llegar a dos de las implementaciones más populares utilizadas en los ambientes industriales: RS485 y Ethernet. Si bien la primera es mucho más antigua, sigue aún vigente y se ha potenciado a partir de la creación de interfaces compatibles, citando como ejemplo la inmunidad a ruido eléctrico que le provee una interfase transparente sobre fibra óptica. La segunda, más moderna, ya fija una tendencia debido a su ubicuidad y amplitud de prestaciones.
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Use of air side economizer for data center thermal managementKumar, Anubhav 11 July 2008 (has links)
Sharply increasing power dissipations in microprocessors and telecommunications systems have resulted in significant cooling challenges at the data center facility level.Energy efficient cooling of data centers has emerged as an area of increasing importance in electronics thermal management.
One of the lowest cost options for significantly cutting the cooling cost for the data center is an airside economizer. If outside conditions are suitable, the airside economizer introduces the outside air into the data center, making it the primary source for cooling the space and hence a source of low cost cooling.
Full-scale model of a representative data center was developed, with the arrangement of bringing outside air.Four different cities over the world were considered to evaluate the savings over the entire year.Results show a significant saving in chiller energy (upto 50%).The limits of relative humidity can be met at the inlet of the server for the proposed design, even if the outside air humidity is higher or lower than the allowable limits.The saving in the energy is significant and justifies the infrastructure improvements, such as improved filters and control mechanism for the outside air influx.
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Hardware mapping of critical paths of a GaAs core processor for solid modelling accelerator / by Song Cui.Cui, Song January 1996 (has links)
Bibliography: leaves 200-207. / xi, 207 leaves : ill. ; 20 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / The aim of this thesis is to design and implement the hardware mapping of critical paths of a GaAs Core Processor for a Solid Modelling Accelerator. The solid modelling accelerator is designed using GaAs/CMOS/B:CMOS unified technology. High speed GaAs technology is used in the core processor to deal with floating point intensive calculations, while CMOS technology is used where high speed outputs are not required. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1996
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Fast asynchronous VSLI circuit design techniques and their application to microprocessor design / Shannon V. Morton.Morton, Shannon V. January 1997 (has links)
Bibliography: leaves 216-224. / xix, 224 leaves : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / This thesis describes a collection of design techniques engineered for high speed operation. A new gate representation is proposed to better reflect their functionality in an asynchronous domain. Two microprocessors (ECSTAC and ECSCESS) are implemented as an illustration of these design techniques. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1998?
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Peptidal processor enhanced with programmable translation and integrated dynamic acceleration logic /Yourst, Matt T. January 2005 (has links)
Thesis (M.S.)--State University of New York at Binghamton, Department of Computer Science, Thomas J. Watson School of Engineering and Applied Science, 2005. / "This dissertation is a compound document (contains both a paper copy and a CD as part of the dissertation)"--ProQuest abstract document view. Includes bibliographical references.
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Activity-aware modeling and design optimization of on-chip signal interconnectsSundaresan, Krishnan. January 2006 (has links)
Thesis (Ph. D.)--Michigan State University. Dept. of Electrical and Computer Engineering, 2006. / Title from PDF t.p. (viewed on Nov. 17, 2008) Includes bibliographical references (p. 183-195). Also issued in print.
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Optimizing XML-based grid services on multi-core processors using an emulation frameworkBhowmik, Rajdeep. January 2007 (has links)
Thesis (M.S.)--State University of New York at Binghamton, Department of Computer Science, Thomas J. Watson School of Engineering and Applied Science, 2007. / Includes bibliographical references.
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An evaluation of CoWare Inc.'s Processor Designer tool suite for the design of embedded processorsFranz, Jonathan D. Duren, Russell Walker. January 2008 (has links)
Thesis (M.S.E.C.E.)--Baylor University, 2008. / Includes bibliographical references (p. 322-323)
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