The purpose of this study was to write a cross-assembler for the Motorola M6800 microcomputer to run on the Data General Nova minicomputer and dual disk hardware. The Nova minicomputer assembly language was selected for the cross-assembler program.Specifications for the cross-assembler were formulated as a hybrid of those of an assembler written by the microcomputer manufacturer, those of the Nova assembler, and some which were dictated by the hardware utilized. A skeletal program was written in which the processing modules were represented as subroutine calls. Subsequently, the processing modules were written and incorporated into the main program. The thesis discusses the M6800 programming language, the cross-assembler specifications, and the resulting implementation.The cross-assembler produced from this research was tested on numerous source programs and performed as specified. Samples of cross-assembler output listings are included in the thesis.Ball State UniversityMuncie, IN 47306

In recent years, with only small fractions of modern processors now accessible in a single cycle, computer architects constantly fight against propagation issues across the die. Unfortunately this trend continues to shift inward, and now the even most internal features of the pipeline are designed around communication, not computation. To address the inward creep of this constraint, this work focuses on the characterization of communication within the pipeline itself, architectural techniques to avoid it when possible, and layout co-design for early detection of problems. I present work in creating a novel detection tool for common case operand movement which can rapidly characterize an applications dataflow patterns. The results produced are suitable for exploitation as a small number of patterns can describe a significant portion of modern applications. Work on dynamic dependence collapsing takes the observations from the pattern results and shows how certain groups of operations can be dynamically grouped, avoiding unnecessary communication between individual instructions. This technique also amplifies the efficiency of pipeline data structures such as the reorder buffer, increasing both IPC and frequency. I also identify the same sets of collapsible instructions at compile time, producing the same benefits with minimal hardware complexity. This technique is also done in a backward compatible manner as the groups are exposed by simple reordering of the binarys instructions. I present aggressive pipelining approaches for these resources which avoids the critical timing often presumed necessary in aggressive superscalar processors. As these structures are designed for the worst case, pipelining them can produce greater frequency benefit than IPC loss. I also use the observation that the dynamic issue order for instructions in aggressive superscalar processors is predictable. Thus, a hardware mechanism is introduced for caching the wakeup order for groups of instructions efficiently. These wakeup vectors are then used to speculatively schedule instructions, avoiding the dynamic scheduling when it is not necessary. Finally, I present a novel approach to fast and high-quality chip layout. By allowing architects to quickly evaluate what if scenarios during early high-level design, chip designs are less likely to encounter implementation problems later in the process.

The main contribution of this dissertation is the demonstration of the impact of a new emerging technology called 3D-integration technology on conventional high-performance microprocessors. 3D-integration technology stacks active devices in the vertical dimension in addition to the conventional horizontal dimension. The additional degree of connectivity in the vertical dimension enables circuit designers to replace long horizontal wires with short vertical interconnects, thus reducing delay, power consumption, and area. To adapt planar microarchitectures to 3D-integrated designs, we study several building blocks that together comprise a substantial portion of a processor s total transistor count. In particular, we focus our attention on three basic circuit classes: static random access memory (SRAM) circuits, associative/CAM logic circuits, and data processing in conventional high-performance processors. We propose 2-die-stacked and 4-die-stacked 3D-integrated circuits to deal with the constraints of the conventional planar technology. We propose high-performance 3D-integrated microprocessors and evaluate the impact on performance, power, and temperature. We demonstrate two different approaches to improve performance: clock speed (3D-integrated processors with identical microarchitectural configurations as the corresponding planar processor run at a higher clock frequency), and IPC (3D-integrated processors accommodate larger-sized modules than the planar processors for the same frequency). We demonstrate the simultaneous benefits of the 3D-integration and highlight the power density and thermal issues related to the 3D-integration technology. Next, we propose microarchitectural techniques based on significance partitioning and data-width locality to effectively address the challenges of power density and temperature. We demonstrate that our microarchitecture-level techniques can effectively control the power density issues in the 3D-integrated processors. The 3D-integrated processors provide a significant performance benefit over the planar processors while simultaneously reducing the total power. The simultaneous benefits in multiple objectives make 3D-integration a highly desirable technology for use in building future microprocessors. One of the key contributions of this dissertation is the temperature analysis that shows that the worst-case temperatures on the 3D-integrated processors can be effectively controlled using microarchitecture level techniques. The 3D-integration technology may extend the applicability of Moore s law for a few more technology generations.

Low-loss off-chip interconnects are required for energy-efficient communication in dense microprocessors. To meet these needs, air cavity parallel plate and microstrip lines with copper conductors were fabricated on an FR-4 epoxy-fiberglass substrate using conventional microelectronics manufacturing techniques. Copper transmission lines were separated by a composite dielectric of air and Avatrel 2000P and by a dielectric layer of air only. The composite dielectric lines were characterized to 10 GHz while the all air dielectric lines were characterized to 40 GHz. The transmission line structures showed loss as low 1.5 dB/cm at 40 GHz with an effective dielectric constant below 1.4. These novel structures show low loss in the dielectric due to the reduced relative permittivity and loss tangent introduced by the air cavity. Transmission line structures with a composite dielectric were built by coating the sacrificial polymer poly(propylene carbonate) (PPC) over a copper signal line, encapsulating with an overcoat polymer, electroplating a ground line, and decomposing PPC to form an air cavity. The signal and ground wires were separated by a layer of 15 µm of air and 20 µm of Avatrel 2000P. Air cavity formation reduced dielectric constant more than 30 percent and loss of less than 0.5 dB/cm was measured at 10 GHz. Residue from PPC decomposition was observed in the cavity of composite dielectric structures and the decomposition characteristics of PPC were evaluated to characterize the residue and understand its formation. Analysis of PPC decomposition based on molecular weight, molecular backbone structure, photoacid concentration and vapor pressure, casting solvent, and decomposition environment was performed using thermogravimetric analysis and extracting kinetic parameters. Novel interaction of copper and PPC was observed and characterized for the self-patterning of PPC on copper. Copper is dissolved from the surface during PPC spincoating and interacts with the polymer chains to improve stability. The improved thermal stability allows selective patterning of PPC on copper. Decomposition characteristics, residual metals analysis, and diffusion profile were analyzed. The unique interaction could simplify air-gap processing for transmission lines. Inorganic-organic hybrid polymers were characterized for use as overcoat materials. Curing characteristics of the monomers and mechanical properties of the polymer films were analyzed and compared with commercially available overcoat materials. The modulus and hardness of these polymers was too low for use as an air-gap overcoat, but may be valuable as a barrier layer for some applications. The knowledge gained from building transmission line structures with a composite dielectric, analyzing PPC decomposition, interaction with copper, and comparison of hybrid polymers with commercial overcoats was used to build air-gap structures with improved electrical design. The ground metal was separated from the signal only by air. The signal wire was supported from above using 60 µm of Avatrel 8000P as an overcoat. Structures showed loss of less than 1.5 dB/cm at 40 GHz, the lowest reported value for a fully encapsulated transmission line structure.

This thesis describes the efficient design of a future many-core processor that can provide higher performance under the limited chip power budget. To achieve such a goal, this thesis first develops an analytical framework within which computer architects can estimate achievable performance improvement of different many-core architectures given the same power budget. From this study, this thesis found that a future many-core processor needs (1) energy-efficient parallel cores and (2) a high-performance sequential core. Based on these observations, this thesis proposes an energy-efficient broad-purpose acceleration layer that can be snapped on top of a conventional general-purpose processor. In addition to such an energy-efficient parallel cores, this thesis also proposes different architectural techniques to further boost the performance of sequential computation while those parallel cores are idle. In particular, this thesis develops low-cost architectural techniques to enhance the memory performance of a host core by utilizing those idle parallel cores. This idea is evaluated in two different system architectures: one with the aforementioned acceleration layer and the other with an emerging integrated CPU and GPU chip.

Thesis (M. Phil.)--University of Hong Kong, 1989.

Not available

This thesis focuses on the logical design of binary adders. It covers topics extending from cardinal numbers to carry skip optimization. The conventional adder designs are described in detail, including: carry completion, ripple carry, carry select, carry skip, conditional sum, and carry lookahead. We show that the method of parallel prefix analysis can be used to unify the conventional adder designs under one parameterized model. The parallel prefix model also produces other useful configurations, and can be used with carry operator variations that are associative. Parallel prefix adder parameters include group sizes, tree shape, and device sizes. We also introduce a general algorithm for group size optimization. Code for this algorithm is available on the World Wide Web. Finally, the thesis shows the derivation for some carry operator variations including those originally given by Majerski and Ling. / text

published_or_final_version / Electrical Engineering / Master / Master of Philosophy

No description available.