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abstract: Ever reducing time to market, along with short product lifetimes, has created a need to shorten the microprocessor design time. Verification of the design and its analysis are two major components of this design cycle. Design validation techniques can be broadly classified into two major categories: simulation based approaches and formal techniques. Simulation based microprocessor validation involves running millions of cycles using random or pseudo random tests and allows verification of the register transfer level (RTL) model against an architectural model, i.e., that the processor executes instructions as required. The validation effort involves model checking to a high level description or simulation of the design against the RTL implementation. Formal techniques exhaustively analyze parts of the design but, do not verify RTL against the architecture specification. The focus of this work is to implement a fully automated validation environment for a MIPS based radiation hardened microprocessor using simulation based approaches. The basic framework uses the classical validation approach in which the design to be validated is described in a Hardware Definition Language (HDL) such as VHDL or Verilog. To implement a simulation based approach a number of random or pseudo random tests are generated. The output of the HDL based design is compared against the one obtained from a "perfect" model implementing similar functionality, a mismatch in the results would thus indicate a bug in the HDL based design. Effort is made to design the environment in such a manner that it can support validation during different stages of the design cycle. The validation environment includes appropriate changes so as to support architecture changes which are introduced because of radiation hardening. The manner in which the validation environment is build is highly dependent on the specifications of the perfect model used for comparisons. This work implements the validation environment for two MIPS simulators as the reference model. Two bugs have been discovered in the RTL model, using simulation based approaches through the validation environment. / Dissertation/Thesis / M.S. Electrical Engineering 2011

Grupos de pesquisa espalhados pelo mundo vêm empregando a Tomografia por Impedância Elétrica (TIE) em aplicações médicas. Entretanto estas pesquisas vem sendo limitadas pelos sistemas de aquisição atualmente empregados, que, frequentemente, n~ao possuem a flexibilidade em termos de números de canais, capacidade de sincronismo temporal e velocidade exigidos nas pesquisas mais recentes. Para facilitar o progresso das pesquisas este trabalho propõe uma arquitetura aberta para aquisição, transferência e armazenamento de sinais. A arquitetura proposta compreende unidades de medição e processamento de sinais, chamadas Canais de Medição. Cada canal de medição é composto por três módulos, o Condicionador de Sinal, o Conversor AD e o Demodulador. Um módulo Supervisor, que essencialmente é um software de configuração e armazenamento, possibilita o controle e monitoramento destes canais através de um módulo Concentrador, que gerencia um barramento de comunicação. Estes módulos, operando em conjunto, têm desempenho equiparável às soluções existentes, porém com ganho de flexibilidade e velocidade. Manutenção e modificações da arquitetura ficam facilitadas pela estrutura modular, aspecto importante nos ambientes de pesquisa. Os dados são armazenados em banco de dados, com a velocidade de coleta compatível com estimação de 50 imagens de TIE por segundo. / Research groups around the world are using Electrical Impedance Tomography (EIT) on medical applications. However investigations are being limited by the acquisition systems, which frequently lack flexibility in terms of the number of channels, temporal synchronism, speed required by recent investigations. To facilitate research progress this work proposes an open architecture for signal acquisition, transfer and storage. The proposed architecture comprises measuring and processing units, called Measuring Channels. Each measuring channel is, in turn, are comprised by three modules, the Signal Conditioner, the AD Converter and the Demodulator. An additional module, called Supervisor, which is essencially an configuration and storage software, allows the monitoring and control of these channels through another additional module, called Concentrator, which manages a communication bus. These modules, working together, have performance equivalent to existing solutions, but with improvements on flexibility and speed. Maintenance and architectural modifications are facilitated due modular structure, important feature in research environment. The data are stored in a database, with data acquisition speed consistent with the estimation of 50 EIT images per second.

Les architectures ''Heterogeneous Many Cores'' (HMC) qui mélangent beaucoup de petits/simples cœurs avec quelques cœurs larges/complexes, fournissent de bonnes performances pour des applications séquentielles et permettent une économie d'énergie pour les applications parallèles. Les petits cœurs des HMC peuvent être utilisés comme des cœurs auxiliaires pour accélérer les applications séquentielles gourmandes en mémoire qui s'exécutent sur le cœur principal. Cependant, le surcoût pour accéder aux petits cœurs limite leur utilisation comme cœurs auxiliaires. En raison de la disparité de performance entre le cœur principal et les petits cœurs, on ne sait pas encore si les petits cœurs sont adaptés pour exécuter des threads auxiliaires pour faire du prefetching pour un cœur plus puissant. Dans cette thèse, nous présentons une architecture hardware/software appelée « core-tethering », pour supporter efficacement l'exécution de threads auxiliaires sur les systèmes HMC. Cette architecture permet au cœur principal de pouvoir lancer et contrôler directement l'exécution des threads auxiliaires, et de transférer efficacement le contexte des applications nécessaire à l'exécution des threads auxiliaires. Sur un ensemble de programmes ayant une utilisation intensive de la mémoire, les threads auxiliaires s'exécutant sur des cœurs relativement petits, peuvent apporter une accélération significative par rapport à du prefetching matériel seul. Et les petits cœurs fournissent un bon compromis par rapport à l'utilisation d'un seul cœur puissant pour exécuter les threads auxiliaires. En résumé, malgré le surcoût lié à la latence d'accès aux lignes de cache chargées par le prefetching depuis le cache L3 partagé, le prefetching par les threads auxiliaires sur les petits cœurs semble être une manière prometteuse d'améliorer la performance des codes séquentiels pour des applications ayant une utilisation intensive de la mémoire sur les systèmes HMC. / Heterogeneous Many Cores (HMC) architectures that mix many simple/small cores with a few complex/large cores are emerging as a design alternative that can provide both fast sequential performance for single threaded workloads and power-efficient execution for through-put oriented parallel workloads. The availability of many small cores in a HMC presents an opportunity to utilize them as low-power helper cores to accelerate memory-intensive sequential programs mapped to a large core. However, the latency overhead of accessing small cores in a loosely coupled system limits their utility as helper cores. Also, it is not clear if small cores can execute helper threads sufficiently in advance to benefit applications running on a larger, much powerful, core. In this thesis, we present a hardware/software framework called core-tethering to support efficient helper threading on heterogeneous many-cores. Core-tethering provides a co-processor like interface to the small cores that (a) enables a large core to directly initiate and control helper execution on the helper core and (b) allows efficient transfer of execution context between the cores, thereby reducing the performance overhead of accessing small cores for helper execution. Our evaluation on a set of memory intensive programs chosen from the standard benchmark suites show that, helper threads using moderately sized small cores can significantly accelerate a larger core compared to using a hardware prefetcher alone. We also find that a small core provides a good trade-off against using an equivalent large core to run helper threads in a HMC. In summary, despite the latency overheads of accessing prefetched cache lines from the shared L3 cache, helper thread based prefetching on small cores looks as a promising way to improve single thread performance on memory intensive workloads in HMC architectures.

In modern deep-scaled CMOS technologies, various silicon-related pitfalls present challenges to the long-term performance of microprocessors. Such challenges include (1) local hot spots, which breach the thermal limitations of a microprocessor, and (2) transistor aging, especially NBTI, which degrades transistor threshold voltage, ultimately threatening the reliability of the entire memory block. In previous systems, the dummy circuit was placed next to the subject, where the dummy was frequently analyzed, and the readout was used to infer the condition of the target. Due to rapidly changing ambient conditions (e.g., temperature and voltage) and the potential scale of the target dimensions, such metrics may not accurately represent the condition of the target. Moreover, such temperature sensors and canary circuits occupy a significant area. Therefore, it would be highly preferable to monitor the target circuit in-situ, i.e., to sense the precise transistor at operation. It is also important to achieve an accurate sensing metric. When the temperature is analyzed, the readout should account for voltage and process variations. While sensing the aging degradation, the readout should account for voltage and temperature fluctuations. This would allow testing during in-field operation, while the circuits achieve area-efficiency. This research had two stages. One result of the first stage was a silicon test chip that was a compact temperature sensor. It involved a family of PTAT+CTAT sensor front-ends that unitized only 6 to 8 conventional CMOS logic devices, yielding a smaller sized chip. The sensor demonstrates accuracy within the target and achieves a 14.3x smaller foot print than preceding published designs. The second product of the first stage was a PMOS aging sensor used in 6T SRAM circuits. The test chip has a real SRAM array, integrated with the proposed PMOS NBTI sensor. It can sense real PMOS NBTI effects in any bit cell (in-situ) and provide robust readings of temperature and voltage (in-field). Intensive aging tests validated the proposed sensing technique. The second stage was focused on implementing the in-situ and in-field sensing techniques in a real processor. The MIPS microprocessor had a modified instruction cache (I$) and instruction set architecture. With the addition of new instruction aging sensing and minor modification of the circuits, the processor can execute aging sensing opportunistically to evaluate the aging level of its instruction cache. A software framework was developed and verified to estimate the retention voltage of the instruction cache over the lifetime of the chip. An area-efficient SoC was developed that could transform the instruction cache into an ambient temperature sensor. It had a physically unclonable function (PUF), and it was built with an area-saving technique similar to the earlier work. This thesis has four chapters. They are presented in chronological and they are aligned with the research described above.

Recent advancements in Large Scale Integration Technology have made available devices, such as microprocessors, analog gates and “three state” logic, that provide the designer with a wide range of possibilities in the design of telecommunication systems. A microprocessor and analog gates are utilized in this design to demonstrate the feasibility of implementing a flexible Telecommunication System. The microprocessor is programmed to control, through software, the system functions. The feasibility of systems highly adaptable to the needs of individual subscribers is thus demonstrated.

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Due to the complexity of designing digital systems using VLSI parts, a tool for aiding in system level design specification and verification is needed. Functional level modeling languages and simulators provide that tool. An example of such a tool is the N.2 package of software produced by Endot Inc. and soon to be running on a VAX computer at the University of Central Florida. An overview of the N.2 system is presented in this paper with emphasis on the modeling language of N.2, ISP’. A Small Instruction set Computer (SIC), originally specified in HAPL, is designed with this software using several design methodologies. These range from an instruction level implementation to a microcoded register level implementation. The ISP’ source code is provided for each implementation. Comments on the ability of the N.2 software to model systems at various levels of design abstraction are made. A comparison of the functional modeling language of N.2, ISP’ to other functional level design languages is made. Finally, some areas that warrant further investigation are presented.