This study analyzes the apologies presented by Intel Corporation as a response to the Pentium™ microprocessor controversy. Dr. Andrew Grove's November 27,1994, Internet posting to the comp.sys.intel usegroup and Intel's December 20,1994, press release are analyzed using the methods of genre criticism. Further, a situational analysis is presented of the exigence and the audience. The exigence is represented by the relationship of society to technology while the audience is Internet users. This analysis attempts to demonstrate how situational factors constrain discourse related to technological flaws.

This thesis describes a software implementation of the IEEE Floating-Point Standard (IEEE Task P754), which is believed to be an effective system for reliable, accurate computer arithmetic. The standard is implemented as a set of procedures written in Motorola 6809 assembly language. Source listings of the procedures are contained in appendices.

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979. / Includes bibliographical references. / by John Edward Pieszcynski. / Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1979.

Non traduit / Semiconductor is one of the most reliable inventions when engineered and used with longevity in mind. However, the increasing demand of fast and highly featured products has drastically changed the reliability realm in the recent years. The means of improving the reliability of nano-metric technology circuits encompass techniques that tackle reliability issues at the level of technology, design and manufacturing. Absolutely necessary but these techniques are almost inevitably imperfect. Therefore, it becomes essential to reduce the consequence of the "remaining" faults using fault tolerance techniques.This thesis focuses on improving and developing new low-power fault tolerance techniques that combine the attractive features of different types of redundancies to tackle permanent and transient faults and addresses the problem of error detection and confinement in modern microprocessor cores. Our case study implementation results show that a power saving of up to 20% can be achieved in comparison with fault tolerance techniques that use only one type of redundancy, and offer low-power lifetime reliability improvement.With the objective to further improve the efficiency in terms of cost and fault tolerance capability we present a design space exploration and an efficient cost-reliability trade-off analysis methodology to selectively harden logic circuits using hybrid fault tolerant techniques. The outcome of the two studies establish that hybrid fault tolerant approaches provide a good foundation for building low-power reliable circuits and systems from future technologies, and our experimental results set a good starting point for further innovative research in this area.

Yau Po Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 91-92). / Abstract also in Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Background --- p.3 / Chapter 2.1 --- Temporal Theories --- p.3 / Chapter 2.2 --- Related Works --- p.4 / Chapter 2.2.1 --- Consistency and Satisfiability of Timing Specifications --- p.4 / Chapter 2.2.2 --- Symbolic Constraint Satisfaction --- p.5 / Chapter 3 --- Previous Developed Work --- p.7 / Chapter 3.1 --- Previous Problem Domain --- p.7 / Chapter 3.1.1 --- Basics of MC68000 Read Cycle --- p.7 / Chapter 3.2 --- Knowledge-based System Structure --- p.9 / Chapter 3.3 --- Diagnostic Reasoning Mechanisms --- p.10 / Chapter 3.4 --- Time Range Approach --- p.11 / Chapter 3.4.1 --- Time Range Representation --- p.11 / Chapter 3.4.2 --- Constraint Satisfaction of Time Ranges --- p.12 / Chapter 3.4.3 --- Constraint Propagation of Time Ranges --- p.13 / Chapter 3.5 --- Fuzzy Time Point Approach --- p.14 / Chapter 3.5.1 --- Fuzzy Time Point Models --- p.14 / Chapter 3.5.2 --- Definition of Fuzzy Time Points --- p.15 / Chapter 3.5.3 --- Constraint Propagation of Fuzzy Time Points --- p.17 / Chapter 3.5.4 --- Constraint Satisfaction of Fuzzy Time Points --- p.18 / Chapter 4 --- The Proposed Segmented Time Range Approach --- p.20 / Chapter 4.1 --- Introduction --- p.20 / Chapter 4.2 --- The Insufficiency of The Existing Time Range Approach --- p.22 / Chapter 4.3 --- Segmented Time Range Approach --- p.23 / Chapter 4.3.1 --- The Representation --- p.23 / Chapter 4.3.2 --- Constraint Propagation and Satisfaction --- p.25 / Chapter 4.3.3 --- Contributions --- p.25 / Chapter 4.3.4 --- Limitations --- p.29 / Chapter 4.4 --- Conclusion --- p.30 / Chapter 5 --- New Problem Domain and Our New System --- p.31 / Chapter 5.1 --- Introduction --- p.31 / Chapter 5.2 --- Pentium-SRAM Interfacing Problem --- p.31 / Chapter 5.2.1 --- Asynchronous SRAM Solution --- p.32 / Chapter 5.2.2 --- Synchronous SRAM Solution --- p.33 / Chapter 5.3 --- The Knowledge Base --- p.35 / Chapter 5.4 --- Characteristics of Our New System --- p.35 / Chapter 6 --- Burst Read Cycle --- p.37 / Chapter 6.1 --- Introduction --- p.37 / Chapter 6.2 --- Asynchronous SRAM Solution --- p.37 / Chapter 6.2.1 --- Implementation --- p.39 / Chapter 6.2.2 --- Implementation Results --- p.45 / Chapter 6.3 --- Synchronous SRAM Solution --- p.48 / Chapter 6.3.1 --- Implementation --- p.49 / Chapter 6.3.2 --- Implementation Results --- p.56 / Chapter 6.4 --- Conclusion --- p.58 / Chapter 7 --- Burst Write Cycle --- p.60 / Chapter 7.1 --- Introduction --- p.60 / Chapter 7.2 --- Asynchronous SRAM Solution --- p.60 / Chapter 7.2.1 --- Implementation --- p.61 / Chapter 7.2.2 --- Implementation Results --- p.67 / Chapter 7.3 --- Synchronous SRAM Solution --- p.71 / Chapter 7.3.1 --- Implementation --- p.71 / Chapter 7.3.2 --- Implementation Results --- p.79 / Chapter 7.4 --- Conclusion --- p.82 / Chapter 8 --- Conclusion --- p.83 / Chapter 8.1 --- Summary of Achievements --- p.83 / Chapter 8.2 --- Future Development --- p.86 / Appendix Some Characteristics of Our New System --- p.89 / Bibliography --- p.91

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING / Includes bibliographical references. / by William Robert Gandler. / M.S.

Thesis (Elec.E)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1981. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Bibliography: leaves 147-148. / by Raleigh Cedric Gallington. / Elec.E

Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING / by Joseph Jay Kesselman Jr. / B.S.

No description available.

O objetivo deste trabalho é analisar o quadro concorrencial do mercado de microprocessadores no setor de informática no Brasil. A regulamentação mercadológica no país apresenta barreiras à entrada e concentração de poder de mercado. Foi aplicado a teoria da concorrência perfeita para explicar a prática do setor e verificou-se que mesmo uma empresa a qual possui o monopólio, não conseguiu prever a mudança no hábito de compra dos consumidores de computadores. A companhia apostou que os seus clientes iriam realizar o refresh das suas máquinas antigas, no entanto devido a entrada de novos produtos como tablets e smartphones, os mesmos optaram por adquirir-los. Tal alternância impactou o posicionamento da empresa a qual precisou reorganizar sua estrutura perante esse novo cenário, pois novos competidores capacitados se anteciparam e preparam-se para essa transformação, tornando-se assim líder no mercado de processadores de dispositivos móveis. / The objective of this study is to analyze the competitive environment of the microprocessor market in the computer industry in Brazil. The marketing regulations in the country presents barriers to entry and market power concentration. It applied the theory of perfect competition to explain the practice of the industry and it was found that even a company which has a monopoly, failed to predict the change in buying habits of computer users. The company bet that its customers would realize the refresh their old machines, however due to entry of new products such as tablets and smartphones, they chose to purchase them. Such fluctuations impacted the company's position which had to reorganize its structure before this new scenario, as new competitors capable anticipated and prepare for this transformation, thus becoming a leader in the mobile processor market.