An application of microcomputer design is given. A microprocessor based system is used to automate the entry logging procedure for a teaching laboratory. The system is used to control entry point security and maintain a laboratory logbook for each entry/exit transaction. A barcode scanner interfaced to the microprocessor identifies users by reading their university ID cards. A permanent record of each entry/exit is made on a magnetic cassette tape. A software package which runs on the university's mainframe computer is used to analyze the entry/exit information. / M. S.

Microprocessors are used in many applications where a high degree of reliability is required. For instance, satellite based systems operating in space have no way being serviced if something were goes wrong. Often these systems, operating in radiation environments, are subject to random high energy particles that pass through the device and upset the operation of the microprocessor for a short period but leave no permanent damage. These transient faults are difficult to predict, prevent, or detect but can lead to a system failure if not discovered. / Master of Science

The real time multitasking systems are becoming increasingly popular for control and monitoring functions typically encountered in industry as well as day to day life. They have to manage adequately many concurrent processes or tasks, each of which is sequential in nature. The concurrency is achieved by running asynchronous tasks at different speeds and providing for communication and synchronization. In order to fully exploit the power and capabilities of today's sophisticated microprocessors and to provide a programming methodology for structuring real time applications a real time multitasking operating system becomes critical. / Master of Science

by Siu Hing Kee Stanley. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves 87-88). / Abstract --- p.ii / Acknowledgments --- p.iii / Chapter 1 --- Introduction --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Background --- p.1-2 / Chapter 1.3 --- Thesis Organization --- p.1-4 / Chapter 2 --- Synthesis of Common Structures in a Microcontroller --- p.2-1 / Chapter 2.1 --- Limitation of Synthesis Tools --- p.2-1 / Chapter 2.2 --- Synthesizable VHDL for Common Structures --- p.2-2 / Chapter 2.2.1 --- Counter --- p.2-3 / Chapter 2.2.2 --- Set-Reset Latch --- p.2-6 / Chapter 2.2.3 --- D Latch --- p.2-9 / Chapter 2.2.4 --- D Flip-flop --- p.2-12 / Chapter 2.2.5 --- Multiplexor --- p.2-13 / Chapter 2.2.6 --- Shift Register --- p.2-15 / Chapter 2.2.7 --- Signal Affected by Two Signal Edges --- p.2-18 / Chapter 2.2.8 --- Combinational Feedback --- p.2-19 / Chapter 2.2.9 --- Short Pulses --- p.2-21 / Chapter 2.2.10 --- Register Transfer Logic --- p.2-22 / Chapter 2.2.11 --- Status Flag --- p.2-26 / Chapter 2.2.12 --- Register Access --- p.2-30 / Chapter 2.2.13 --- Clock Divider --- p.2-34 / Chapter 2.2.14 --- Communication among Processes --- p.2-36 / Chapter 3 --- Synthesis of Components of a Microcontroller --- p.3-1 / Chapter 3.1 --- Timer --- p.3-1 / Chapter 3.2 --- Serial Peripheral Interface (SPI) --- p.3-9 / Chapter 3.3 --- Serial Communication Interface (SCI) --- p.3-16 / Chapter 3.4 --- Parallel I/O Port --- p.3-21 / Chapter 3.5 --- 6805CPU --- p.3-22 / Chapter 3.5.1 --- State Counter --- p.3-23 / Chapter 3.5.2 --- Instruction Decoding and Execution Unit --- p.3-24 / Chapter 3.5.3 --- Interrupt Logic --- p.3-25 / Chapter 3.5.4 --- Instruction Register --- p.3-27 / Chapter 4 --- VHDL Coding and Synthesis --- p.4-1 / Chapter 4.1 --- Controlling Synthesis by VHDL Coding --- p.4-1 / Chapter 4.1.1 --- Structure Control --- p.4-2 / Chapter 4.1.2 --- Feedback Path Control --- p.4-2 / Chapter 4.1.3 --- Control of Use of Storage --- p.4-2 / Chapter 4.1.4 --- Timing Control --- p.4-3 / Chapter 4.2 --- Consequences of the Writing Guidelines --- p.4-5 / Chapter 5 --- Interface Tool for Generation of VHDL for a Microcontroller --- p.5-1 / Chapter 5.1 --- Features --- p.5-1 / Chapter 5.2 --- Construction --- p.5-1 / Chapter 5.3 --- Illustration --- p.5-3 / Chapter 5.4 --- Data Structure --- p.5-5 / Chapter 5.4.1 --- Design List --- p.5-6 / Chapter 5.4.2 --- Instance Data --- p.5-6 / Chapter 5.4.3 --- Instance List --- p.5-8 / Chapter 5.4.4 --- Register Data --- p.5-9 / Chapter 5.4.5 --- Dialogs and Functions --- p.5-10 / Chapter 5.5 --- VHDL Generator for Individual Component --- p.5-11 / Chapter 5.6 --- VHDL Generator for the Whole Microcontroller --- p.5-14 / Chapter 6 --- Conclusion --- p.6-1 / Bibliography --- p.B-1 / Appendix --- p.A-1

Exploiting better performance from computer programs translates to finding more instructions to execute in parallel. Since most general purpose programs are written in an imperatively sequential manner, closely lying instructions are always data dependent, making the designer look far ahead into the program for parallelism. This necessitates wider superscalar processors with larger instruction windows. But superscalars suffer from three key limitations, their inability to scale, sequential fetch bottleneck and high branch misprediction penalty. Recent studies indicate that current superscalars have reached the end of the road and designers will have to look for newer ideas to build computer processors. Speculative Multithreading (SpMT) is one of the most recent techniques to exploit parallelism from applications. Most SpMT architectures partition a sequential program into multiple threads (or tasks) that can be concurrently executed on multiple processing units. It is desirable that these tasks are sufficiently distant from each other so as to facilitate parallelism. It is also desirable that these tasks are control independent of each other so that execution of a future task is guaranteed in case of local control flow misspeculations. Some task prediction mechanisms rely on the compiler requiring recompilation of programs. Current dynamic mechanisms either rely on program constructs like loop iterations and function and loop boundaries, resulting in unbalanced loads, or predict tasks which are too short to be of use in an SpMT architecture. This thesis is the first proposal of a predictor that dynamically predicts control independent tasks that are consistently wide apart, and executes them on a novel SpMT architecture.

Typescript (photocopy). / Digitized by Kansas Correctional Industries

Call number: LD2668 .T4 1979 K56 / Master of Science

Call number: LD2668 .T4 1984 A42 / Master of Science

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / The availability of high density FPGAs has made the use of soft-core processors an attractive proposition for the low volume space market. Soft-core processors combine the power of programmable logic with the ease of use of a conventional processor to provide a highly customisable solution. However, the SRAM FPGAs used as implementation platform are especially susceptable to radiation induced single event upsets, due to the sensitivity of their configuration memory. To safely use these processors in a space environment requires the modification of the processor to safely mitigate these effects. This thesis presents the process followed to develop and test a fault tolerant implementation of an 8-bit PicoBlaze soft-core processor on a Xilinx Spartan-3 SRAM FPGA. A thorough investigation was made into the available methods that can be used to mitigate single event upsets, in order to identify the most suitable ones. Guidelines for the application of SEU mitigation techniques to SRAM FPGAs were proposed. A single event upset simulator was designed and constructed to compare the different techniques. It mimics SEUs by injecting errors into the configuration memory of an FPGA. The results of error injection were used to develop a PicoBlaze implementation with limited overhead, while it still offers a high degree of error mitigation. Three different designs were tested by proton irradiation to verify the protection afforded by the mitigation techniques. It was found that protected designs were more robust. The cross-section of the FPGA was also determined, which can be used with the SEU simulator to predict the dynamic cross-section of designs. The work contained in this thesis demonstrates the use of open-source intellectual property with commercial-off-the-shelf components to develop a robust component for use in the miniature spacecraft market.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy