Much of guitarist Wes Montgomery’s study of jazz improvisation came from imitating Charlie Christian’s guitar solos. The purpose of this study is to identify and examine significant improvisational traits that Wes Montgomery developed as a direct result of his imitation and assimilation of Charlie Christian. The dissertation investigates the musical traditions in Christian’s playing that were absorbed into Montgomery’s playing and how Montgomery was able to use these traits to foster new musical traditions. The solo transcriptions are limited to Montgomery’s early recordings between 1957 and ending with his 1960 album The Incredible Jazz Guitar of Wes Montgomery. The study also examines the relationship imitation has with creativity in jazz and how originality is influenced by the past. The dissertation examines the two guitarists’ use of five harmonic and melodic devices over dominant harmonies: scales, arpeggios, use of chromatic pitches, formulas and enclosures, and harmonic substitutions. The study focuses on how Montgomery’s melodic and harmonic treatment of dominant harmonies has been influenced by his imitation and assimilation of Christian’s improvisations. The study examines how Montgomery differentiated himself in his improvisations from Christian’s. A strong emphasis is given to the significance of these differences and how these differences are connected to Montgomery’s originality and innovation. This dissertation confirms that Montgomery’s innovation was strongly linked to his imitation of Charlie Christian. It also suggests that devotion to the imitation of past artists is needed in developing an original voice in jazz. / Biographical history and musical development of Charlie Christian -- Biographical history and musical development of Wes Montgomery -- Stylistic traits of Charlie Christian over dominant-seventh harmonies -- Stylistic traits of Wes Montgomery influenced by Charlie Christian -- Conclusion. / School of Music

An important advantage of Elliptic Curve Cryptosystem (ECC) is the shorter key length in public key cryptographic systems. It can provide adequate security when the bit length over than 160 bits. Therefore, it has become a popular system in recent years. Scalar multiplication also called point multiplication is the core operation in ECC. In this thesis, we propose the ECC architectures of two different irreducible polynomial versions that are trinomial in GF(2167) and pentanomial in GF(2163). These architectures are based on Montgomery point multiplication with projective coordinate. We use polynomial basis representation for finite field arithmetic. All adopted multiplication, square and add operations over binary field can be completed within one clock cycle, and the critical path lies on multiplication. In addition, we use Itoh-Tsujii algorithm combined with addition chain, to execute binary inversion through using iterative binary square and multiplication. Because the double and add operations in point multiplication need to run many iterations, the execution time in overall design will be decreased if we can improve this partition. We propose two ways to improve the performance of point multiplication. The first way is Minus Cycle Version. In this version, we reschedule the double and add operations according to point multiplication algorithm. When the clock cycle time (i.e., critical path) of multiplication is longer than that of add and square, this method will be useful in improving performance. The second way is Pipeline Version. It speeds up the multiplication operations by executing them in pipeline, leading to shorter clock cycle time. For the hardware implementation, TSMC 0.13um library is employed and all modules are organized in a hierarchy structure. The implementation result shows that the proposed 167-bit Minus Cycle Version requires 156.4K gates, and the execution time of point multiplication is 2.34us and the maximum speed is 591.7Mhz. Moreover, we compare the Area x Time (AT) value of proposed architectures with other relative work. The results exhibit that proposed 167-bit Minus Cycle Version is the best one and it can save up to 38% A T value than traditional one.

In asymmetric cryptosystems, an important advantage of Elliptic Curve Cryptosystem (ECC) is the shorter key lengths than other cryptosystems. It can provide a level of security when the bit length over than 160 bits. So it has become a popular public key cryptographic system in recent year. Multiplier needs to run many times in scalar multiplication and it plays an essential role in ECC. Since the registers in multiplier are shifted every iteration, it will consume a lot of power in the computing process. So in this thesis, we propose five methods to save multiplication¡¦s energy consumption based on a scalable serial-parallel algorithm[1]. The first method is to design a low-power shift-register by modifying shift-register B to reduce the frequency of registers shifted. The second method is to use a frequency divider circuit. It can make registers to access a value every two clock cycles by modifying RA units. The third method is to introduce the gated clock circuit, and the clock signal of register will be disabled if its value is the same. The fourth method is to skip redundant operations and it can decrease the number of clock cycles for completing a multiplication operation. The last method raises multiplier¡¦s throughput by modifying RA units. The former three methods focus on low-power design, and the latter two methods emphasize on improving performance. Reducing power consumption and improving performance will save multiplication¡¦s energy consumption. Finally, we propose a Half Cycles schedule to raise scalar multiplication¡¦s performance. It is based on Montgomery scalar multiplication algorithm with projective coordinate[22][26]. For the hardware implementation, TSMC 0.13um library is employed and all modules are organized in a hierarchy structure. The implementation results show that the proposed multipliers have less energy consumption than traditional multiplier. It can get 5% ~ 24% energy saving. For Montgomery scalar multiplication, it can also reduce 12% ~ 47% energy consumption and is suitable for portable electronic products because its low area complexity and low energy.

Reproduction de : Thèse de doctorat : Informatique : Paris 8 : 2007. / Titre provenant de l'écran-titre. Bibliogr. p. 133-137.

The primary objective of this M.A. Thesis is to provide an in-depth comparison of Heidi and Anne of Green Gables by: (1) revealing through a literary and social analysis, the more somber aspects of these novels. (2) examining the multi-dimensionality of the characters found therein and (3) investigating the possible reasons for the mythical and legendary proportions of these tales. In doing so, I hope to clarify the misconception that these novels, as children's books, are based solely on idealistic and light-hearted themes. Further, I would like to answer, in part, why these two orphan tales have remained so universally popular for so long, whereas other similar books have not. But most of all, I hope to prove that children's literature has significant literary merit, worthy of academic interest and investigation.

This thesis is the real time implementation of the new, unified field, dual&ndash / radix Montgomery modular multiplier architecture presented by SavaS et al, for performance comparison with standard Montgomery multiplication algorithms. The unified field architecture operates in both GF(p) and GF(2n). The dual radix capability enables processing of two bits of the multiplier in every clock cycle in GF(2n) mode, while one bit of the multiplier is processed in GF(p) mode. The new architecture is implemented in a Xilinx FPGA on the custom printed circuit board. The windows user interface is developed in Borland Builder environment and the ethernet interface is implemented by Ubicom IP2022 controller. The algorithms are compared from operating clock frequency, silicon area cost and multiplication time perspectives. The new architecture multiplies two times faster in GF(p) and four times faster in GF(2n), compared to the previous architectures as expected. The operand length is increased from 8 bits to 1024 bits, with the compromise of decreasing the operating clock frequency from 150 Mhz down to 15 Mhz.

Project report (D. Min.)--New Orleans Baptist Theological Seminary, 1998. / Abstract and vita. Includes bibliographical references (leaves 86-92).

Project report (D. Min.)--New Orleans Baptist Theological Seminary, 1998. / Abstract and vita. Includes bibliographical references (leaves 86-92).

Project report (D. Min.)--New Orleans Baptist Theological Seminary, 1998. / Abstract and vita. Includes bibliographical references (leaves 86-92).

Thesis (M.A.)--Cincinnati Christian Seminary, 1987. / Typescripts. Abstract. Includes bibliographical references (leaves 166-177).