Une tendance importante dans le domaine de l’embarqué est l’intégration de plus en plus d’éléments de calcul dans les systèmes multiprocesseurs sur puce (MPSoC). Cette tendance est due en partie aux limitations des puissances individuelles de ces éléments causées par des considérations de consommation d’énergie. Dans le même temps, en raison de leur sophistication croissante, les applications de traitement du signal ont des besoins en puissance de calcul de plus en plus dynamique. Dans la conception et le développement d’applications de traitement de signal multicoeur, l’un des principaux défis consiste à répartir efficacement les différentes tâches sur les éléments de calcul disponibles, tout en tenant compte des changements dynamiques des fonctionnalités de l’application et des ressources disponibles. Une utilisation inefficace peut conduire à une durée de traitement plus longue et/ou une consommation d’énergie plus élevée, ce qui fait de la répartition des tâches sur un système multicoeur une tâche difficile à résoudre. Les modèles de calcul (MoC) flux de données sont communément utilisés dans la conception de systèmes de traitement du signal. Ils décomposent la fonctionnalité de l’application en acteurs qui communiquent exclusivement par l’intermédiaire de canaux. L’interconnexion des acteurs et des canaux de communication est modélisée et manipulée comme un graphe orienté, appelé un graphique de flux de données. Il existe différents MoCs de flux de données qui offrent différents compromis entre la prédictibilité et l’expressivité. Ces modèles de calculs sont communément utilisés dans la conception de systèmes de traitement du signal en raison de leur analysabilité et leur expressivité naturelle du parallélisme de l’application. Dans cette thèse, une nouvelle méthode de répartition de tâches est proposée afin de répondre au défi que propose la programmation multicoeur. Cette méthode de répartition de tâches prend ses décisions en temps réel afin d’optimiser le temps d’exécution global de l’application. Les applications sont décrites en utilisant le modèle paramétrée et interfacé flux de données (PiSDF). Ce modèle permet de décrire une application paramétrée en autorisant des changements dans ses besoins en ressources de calcul lors de l’exécution. A chaque exécution, le modèle de flux de données paramétré est déroulé en un modèle intermédiaire faisant apparaitre toute les tâches de l’application ainsi que leurs dépendances. Ce modèle est ensuite utilisé pour répartir efficacement les tâches de l’application. La méthode proposé a été testée et validé sur plusieurs applications des domaines de la vision par ordinateur, du traitement du signal et du multimédia. / An important trend in embedded processing is the integration of increasingly more processing elements into Multiprocessor Systemson- Chip (MPSoC). This trend is due in part to limitations in processing power of individual elements that are caused by power consumption considerations. At the same time, signal processing applications are becoming increasingly dynamic in terms of their hardware resource requirements due to the growing sophistication of algorithms to reach higher levels of performance. In design and implementation of multicore signal processing systems, one of the main challenges is to dispatch computational tasks efficiently onto the available processing elements while taking into account dynamic changes in application functionality and resource requirements. An inefficient use can lead to longer processing times and higher energy consumption, making multicore task scheduling a very difficult problem to solve. Dataflow process network Models of Computation (MoCs) are widely used in design of signal processing systems. It decomposes application functionality into actors that communicate data exclusively through channels. The interconnection of actors and communication channels is modeled and manipulated as a directed graph, called a dataflow graph. There are different dataflow MoCs which offer different trade-off between predictability and expressiveness. These MoCs are widely used in design of signal processing systems due to their analyzability and their natural parallel expressivity. In this thesis, we propose a novel scheduling method to address multicore scheduling challenge. This scheduling method determines scheduling decisions strategically at runtime to optimize the overall execution time of applications onto heterogeneous multicore processing resources. Applications are described using the Parameterized and Interfaced Synchronous DataFlow (PiSDF) MoC. The PiSDF model allows describing parameterized application, making possible changes in application’s resource requirement at runtime. At each execution, the parameterized dataflow is then transformed into a locally static one used to efficiently schedule the application with an a priori knowledge of its behavior. The proposed scheduling method have been tested and benchmarked on multiple state-of-the-art applications from computer vision, signal processing and multimedia domains.

As limitações resultantes do avanço das tecnologias de integração, como o crescente aumento da densidade de potência, levando à necessidade de redução da frequência de operação dos circuitos somados à necessidade de redução do consumo energético, sejam por motivos ecológicos ou para melhor suprir dispositivos portáteis, trazem a necessidade de maior intervenção e personalização do hardware em relação às exigências do software. Em diversos níveis estas intervenções podem ser aplicadas, onde a granularidade pode variar desde elementos de processamento sendo completamente desativados até processadores tendo apenas unidades funcionais sendo desativadas, memórias cache reconfiguradas em tamanho e associatividade, etc. Entretanto, a reconfiguração do hardware deve atingir todas as etapas destes sistemas para que seja possível atingir redução satisfatória em termos de potência e consumo de energia. Além da integração acelerada de elementos de processamento em um mesmo circuito integrado, a crescente concentração de heterogêneas tarefas em um mesmo dispositivo, leva à integração de elementos de processamento também heterogêneos, e por consequência diferentes comportamentos variando de acordo com a aplicação. Para justificar esta reconfigurabilidade e heterogeneidade dos elementos de processamento este trabalho apresenta um estudo que possibilita a observação da execução de diferentes aplicações em elementos de processamento amplamente reconfiguráveis. Para que a reconfigurabilidade e heterogeneidade possam ser aplicáveis, foi inserida uma ferramenta capaz de manter a compatibilidade entre o elemento de processamento mestre e os elementos de processamento aceleradores reconfiguráveis disponíveis. Os experimentos apresentados baseiam-se na necessidade de manter a menor quantidade de silício ativa, acelerando o código fonte enquanto reduz-se o consumo de energia. Somada a redução de energia, a compatibilidade binária é levada em consideração buscando a manutenção da produtividade quando da utilização de sistemas heterogêneos reconfiguráveis. / The limitations resulting from the advancement of integration technologies, such as the increasing power density, leading to the need to reduce the operating frequency of the circuits added to the need to reduce energy consumption, whether for environmental reasons or to better serve mobile devices, bring the need for greater intervention and hardware customization to the demands of the software. To varying degrees these interventions can be applied where the granularity can range from processing elements being completely disabled until processors having only functional units being disabled, reset cache memories in size and associativity, etc. However, the reconfiguration of hardware should reach all stages of these systems so that you can achieve satisfactory reduction in power and energy consumption. In addition to the accelerated integration of processing elements on a single integrated circuit, the increasing concentration of heterogeneous tasks in a same device, also leads to the integration of heterogeneous processing elements, and therefore different behavior varies according to the application. To justify this reconfigurability and variety of processing elements this work presents a study that allows the observation of the implementation of different applications in widely reconfigurable processing elements. For reconfigurability and heterogeneity may be applicable, a tool to maintain compatibility between the master processing element and accelerators reconfigurable processing elements available was inserted. The experiments presented are based on the need to maintain the lowest amount of active silicon, accelerating the source code while reducing power consumption. Added to energy reduction, binary compatibility is taken into consideration seeking to maintain productivity when using reconfigurable heterogeneous systems.

Thesis: M.S., Massachusetts Institute of Technology, Department of Aeronautics and Astronautics, 1976 / Bibliography: p.110. / by Charles E. Manush, III. / M.S. / M.S. Massachusetts Institute of Technology, Department of Aeronautics and Astronautics

Commodity hypervisors are widely deployed to support virtual machines on multiprocessor server hardware. Modern hypervisors are complex and often integrated with an operating system kernel, posing a significant security risk as writing large, multiprocessor systems software is error-prone. Attackers that successfully exploit hypervisor vulnerabilities may gain unfettered access to virtual machine data and compromise the confidentiality and integrity of virtual machine data. Theoretically, formal verification offers a solution to this problem, by proving that the hypervisor implementation contains no vulnerabilities and protects virtual machine data under all circumstances. However, it remains unknown how one might feasibly verify the entire codebase of a complex, multiprocessor commodity system. My thesis is that modest changes to a commodity system can reduce the required proof effort such that it becomes possible to verify the security properties of the entire system. This dissertation introduces microverification, a new approach for formally verifying the security properties of commodity systems. Microverification reduces the proof effort for a commodity system by retrofitting the system into a small core and a set of untrusted services, thus making it possible to reason about properties of the entire system by verifying the core alone. To verify the multiprocessor hypervisor core, we introduce security-preserving layers to modularize the proof without hiding information leakage so we can prove each layer of the implementation refines its specification, and the top layer specification is refined by all layers of the core implementation. To verify commodity hypervisor features that require dynamically changing information flow, we incorporate data oracles to mask intentional information flow. We can then prove noninterference at the top layer specification and guarantee the resulting security properties hold for the entire hypervisor implementation. Using microverification, we retrofitted the Linux KVM hypervisor with only modest modifications to its codebase. Using Coq, we proved that the hypervisor protects the confidentiality and integrity of VM data, including correctly managing tagged TLBs, shared multi-level page tables, and caches. Our work is the first machine-checked security proof for a commodity multiprocessor hypervisor. Experimental results with real application workloads demonstrate that verified KVM retains KVM’s functionality and performance.

Bibliography: pages 104-110. / Two technologies, distributed operating systems and UNIX are very relevant in computing today. Many distributed systems have been produced and many are under development. To a large extent, distributed systems are considered to be the only way to solve the computing needs of the future. UNIX, on the other hand, is becoming widely recognized as the industry standard for operating systems. The transputer, unlike. UNIX and distributed systems is a relatively new innovation. The transputer is a concurrent processing machine based on mathematical principles. Increasingly, the transputer is being used to solve a wide range of problems of a parallel nature. This thesis combines these three aspects in creating a distributed implementation of UNIX on a network of transputers. The design is based on the satellite model. In this model a central controlling processor is surrounded by worker processors, called satellites, in a master/ slave relationship.

Bibliography: pages 90-94. / The DISTRIX operating system is a multiprocessor distributed operating system based on UNIX. It consists of a number of satellite processors connected to central servers. The system is derived from the MINIX operating system, compatible with UNIX Version 7. A remote procedure call interface is used in conjunction with a system wide, end-to-end communication protocol that connects satellite processors to the central servers. A cached file server provides access to all files and devices at the UNIX system call level. The design of the file server is discussed in depth and the performance evaluated. Additional information is given about the software and hardware used during the development of the project. The MINIX operating system has proved to be a good choice as the software base, but certain features have proved to be poorer. The Inmos transputer emerges as a processor with many useful features that eased the implementation.

No description available.

Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic mapping scheme over the fixed one. Results show that applications’ performance varies according to the mapping scheme used, and a dynamic mapping scheme achieves up to 2x increase in peak bandwidth utilization and around 30% higher energy efficiency than a system using only a single fixed scheme Moreover, the technique can be used to limit memory accesses into a subset of the memory devices by controlling data allocation at a finer granularity, providing a method to throttle main memory by allowing unaccessed devices to be put into power-down mode, hence saving power to meet a certain power budget.

No description available.

Parsing in a multiprocessor environment is considered. Two models for asynchronous bottom-up parallel parsing are presented. A method for estimating speedup in asynchronous bottom-up parallel parsing is developed, and it is used to estimate speedup obtainable by bottom-up parallel parsing of Pascal-like languages. It is found that bottom-up parallel parsing algorithms can attain a maximum speedup of 0 (L1/2) with (L1/2) processors, where L is the number of tokens in the string being parsed. Hence, bottom-up parallel parsing technique does not yield good speedup. A new parsing technique is proposed for parsing a class of block-structured languages. The novelty of the technique is that it is inherently parallel. By applying this new technique, a string of L tokens can be parsed in O (log L) time with (L /log L) processors. The parsing algorithm uses a parenthesis-matching algorithm developed here. The parenthesis-matching algorithm can find matching of a sequence of parentheses in O (log L) time with (L /log L) processors. Thus, the new parsing algorithm is cost optimal.