In this thesis, we will investigate the degradation of the Low-Temperature-Polycrystalline-Silicon TFTs(LTPS TFTS) under the electrical stress. The devices are offer by Chi Mei Optoelectronics. The two mechanisms of the electrical stress are AC and DC stress. On the AC stress, there are some phenomena which cannot be completely explained by typical NBTI mechanism in the experiment. In addition to NBTI, we suggest that the self-heating effect might be involved, because the self-heating effect could rise channel temperature and cause the dissociation of the Si-H bonds at the poly-Si/SiO2 interface due to the Joule heating. We also compare pulse to give on the degradation difference of different place. On the DC stress, we show the stress drain voltage dependence of on-current and threshold voltage degradation, in which the stress gate voltage was fixed at -15V and stress time was 2154 s. The electric measurements of forward and reverse modes were employed to analyze the experimental data. The anomalous negative bias temperature instability degradation of poly-Si TFTs was investigated.

In this thesis, in order to eliminate process issue, an external mechanical uniaxial tensile and compressive stress applied on p-type metal-oxide-semiconductor field effect transistors (p-MOSFETs) is used for the study of negative bias temperature instability (NBTI) characteristics. Drain current and hole mobility decreases under uniaxial tensile strain, and the NBTI characteristics also become more serious simultaneously. And drain current and hole mobility increases under uniaxial compressive strain, and the NBTI characteristics also become less serious simultaneously. By analyzing split capacitance-voltage (C-V) characteristics, inversion charge increases and decreases due to strain induced change of band splitting and effective mass under uniaxial tensile strain and uniaxial compressive strain, respectively. According to Reaction-Diffusion model, interface trap generation rate is proportional to the number of holes in inversion layer. Therefore, the worse NBTI degradation resulted from increased inversion charge induced by uniaxial tensile strain. And the better NBTI degradation resulted from decreased inversion charge induced by uniaxial compressive strain.

L’électronique embarquée dans l’aéronautique, couramment appelé avionique, est chargée d’effectuer des tâches critiques et doit présenter une fiabilité élevée. La technologie Complementary Metal Oxyde Semiconductor (CMOS) est couramment utilisée pour réaliser des composants critiques, comme des mémoires. Les composants CMOS sont susceptibles à deux types d’erreurs : les dégradations liées au vieillissement et les évènements singuliers causés par les particules cosmiques. Or, les conditions d’utilisation de l’avionique renforcent la fréquence d’occurrence de ces deux types d’erreurs. Le vieillissement consiste, pour les composants CMOS, en la dégradation de ses interfaces métal/oxyde et oxyde/semi-conducteur au cours de sa durée de vie. Les composants avioniques subissent un vieillissement accéléré de par leur condition d’utilisation intensive. Le rayonnement cosmique est composé de particules énergétiques d’origine extrasolaire. Certaines de ces particules sont susceptibles d’interagir un composant électronique et d’y déposer de l’énergie, cela peut causer une erreur appelée évènement singulier. L’avionique est particulièrement concernée par cette problématique car ces évènements peuvent être critiques et qu’elle rencontre un flux élevé de particules.Auparavant, la sensibilité aux radiations était considérée comme indépendante du vieillissement. Seulement, les évolutions des technologies CMOS nous amènent à remettre en cause cette hypothèse. Afin d’étudier ce nouveau phénomène, une méthode de modélisation a été développée. Celle-ci couple la modélisation des évènements singuliers à une modélisation électrique circuit du vieillissement. Elle permet d’effectuer des simulations sur un circuit mémoire spécifique dans des environnements radiatifs variés. De ces simulations ressortent l’influence de certains paramètres électriques, qui permettent de proposer une simulation opérationnelle appliquée à l’avionique. / CMOS technologies used in avionics are prone to both aging and soft error caused by cosmic rays. The ongoing technology scaling has improved the radiation sensitivity of memory cells while the contribution of degradations mechanisms remained unchanged. Considering this trend, the hypothesis that radiation sensitivity does not change over the lifetime of a component must be challenged. In order to do so, a modelling methodology is proposed. It is based on an existing radiation modelling device and includes an electrical aging modelling. This modelling is used to characterize the aging impact on radiation sensitivity of several memory cells under different radiative environment. The impact of diverse electrical parameters is noted and an operative avionics study is finally proposed.

Submitted by PPG Engenharia El?trica (engenharia.pg.eletrica@pucrs.br) on 2017-10-03T14:30:54Z No. of bitstreams: 1 dissertacao_Marco_tulio.pdf: 5515221 bytes, checksum: 0531f41d66bffa4a34ad4958a41c2d61 (MD5) / Approved for entry into archive by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-10-04T13:10:44Z (GMT) No. of bitstreams: 1 dissertacao_Marco_tulio.pdf: 5515221 bytes, checksum: 0531f41d66bffa4a34ad4958a41c2d61 (MD5) / Made available in DSpace on 2017-10-04T13:17:57Z (GMT). No. of bitstreams: 1 dissertacao_Marco_tulio.pdf: 5515221 bytes, checksum: 0531f41d66bffa4a34ad4958a41c2d61 (MD5) Previous issue date: 2016-05-27 / With advances in technology and miniaturization of CMOS, reliability during the life cycle of Integrated Circuit (IC) becomes a complex concern for critical applications. Miniaturization brings many benefits as high performance, power consumption and increase number of functions inside of IC. However, alongside with these, the benefits for increase of interconnections and density of such SoCs create new challenges for the industry. Moreover, a chip needs to store more and more information, resulting in the fact that SRAM occupy the greatest part of SoCs. Consequently, technology advances need to increase the transistor?s density, turnning them a critical concern for testing and reliability to be analysed after manufacturing, since it creates new types of defects. Defects during manufacture process, as well as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI) and Electromagnetic Interference (EMI) phenomena represent important challenges that must be addressed at an early stages and over the IC?s life-time. In this context, understanding these phenomena and how they affect technologies below 65nm is essential to ensure reliability required for critical applications. In addition, another source of defects is related to process variations during manufacture. Such defects, like resistive-open and resistive-bridge, appear as the most incident. These defects occur due to small geometric changes in the cell, resulting in static and dynamic failures. Depending on the size of defect they can be considered as weak-defects, which do not result in faulty behaviour at logic level and are not sensitized in conventional manufacturing tests. Note that dynamic faults are considered most responsible for testescapes during manufacturing test. Another important phenomena that affects the reliability of ICs over time is NBTI, causing the aging of SRAMs. In this context, this work proposes to analyze the impact of NBTI in SRAM cells with weak resistive-open and resistive-bridge defects that can escape manufacturing tests due to their dynamic behaviour but, with aging, may become dynamic faults over time. / Com o avan?o tecnol?gico e a miniaturiza??o da tecnologia CMOS, garantir a confiabilidade durante a vida ?til de Circuitos Integrados (CI) tem se tornado um ponto extremamente complexo e importante para aplica??es consideradas cr?ticas. Muitos s?o os benef?cios que esses avan?os trouxeram, como aumento do desempenho, frequ?ncia de opera??o, CIs com capacidade para novas e mais complexas funcionalidades entre outros. Entretanto, com o aumento do n?mero de interconex?es e densidade dos System-on-chip (SoC) novos desafios surgiram e necessitam ser solucionados para que estes avan?os possam continuar. Avan?os tecnol?gicos possibilitaram a fabrica??o de componentes com uma maior densidade de transistores em uma pequena ?rea de sil?cio, tornando-se um ponto cr?tico para o teste e an?lise da confiabilidade ap?s sua fabrica??o, uma vez que esse processo de fabrica??o gera novos tipos de defeitos. Neste sentido, defeitos do tipo resistive-open e resistive-bridge aparecem como os mais prov?veis. Esses defeitos ocorrem devido a pequenas mudan?as geom?tricas das c?lulas e podem causar falhas est?ticas, bem como falhas din?micas. Da mesma forma, fen?menos como Negative Bias Temperature Instability (NBTI), Positive Bias Temperature Instability (PBTI), Hot Carrier Injection (HCI) e Electromagnetic Interference (EMI) representam importantes desafios que obrigatoriamente devem ser tratados desde a fase inicial de projeto de CIs, bem como durante toda a sua vida ?til. Assim, compreender esses fen?menos e como os mesmos afetam tecnologias abaixo de 65nm ? considerado fundamental a fim de garantir a confiabilidade exigida para aplica??es consideradas cr?ticas. Neste contexto, esse trabalho visa avaliar o impacto de defeitos resistivos do tipo resistiveopen e resistive-bridge nas c?lulas de mem?ria do tipo 6T, que passaram nos testes de manufatura, mas que, ao longo dos anos manifestaram falha devido a presen?a do fen?meno de NBTI. Esses defeitos foram modelados atrav?s da inser??o de resist?ncias em determinados pontos da c?lula de mem?ria. Foi observado que defeitos do tipo resistive-open e resistive-bridge quando presentes entre os inversores de uma c?lula de mem?ria e n?o detectados durante os testes de manufatura, resultaram em falha nas opera??es de leitura da c?lula ao longo dos anos quando na presen?a de NBTI. Essa falha apresenta-se inicialmente com um comportamento din?mico e, de acordo com o envelhecimento da c?lula, passa a comporta-se como est?tica. Essa situa??o compromete a confiabilidade da c?lula, uma vez que o tempo de vida estimado da c?lula ser? inferior ao projetado.

Flux trapping and cycling energy losses were studied by vibrating sample magnetometry in fine multifilamentary Nb-Ti superconductive strands for which proximity effect coupling between the filaments is significant. Measurements were made to determine the influence of helical twist about the strand axis as well as sample length for strands experiencing varying levels of proximity effect coupling. The proximity effect strength was varied by investigating strands with a range of filament diameters, as well as by the addition of magnetic impurities to the interfilamentary medium (the matrix) to suppress the proximity effect. Critical currents and fields for the matrix were extracted from the measurements. The reduction of cycling loss1 and magnetization2 previously found was confirmed. Additionally, these measurements were extended to strands where little twist was applied, and the magnetization and cyclic loss were found to saturate. Bean-like models for anisotropic media introduced by Carr1 and later Harada2 were further developed to calculate magnetization and penetration fields in these strands over a large range of twist pitch values. A calculation of magnetic hysteresis loops was also made for short strand samples. These models provide a good qualitative understanding of the observed behavior and lead to useful predictions for applications. / Department of Energy

Invasive and non-invasive methods of BTI monitoring and wearout preemption have been proposed. We propose a novel, simple to use, test structure for NBTI /PBTI monitoring. The proposed structure has an AC and a DC stress mode. Although during stress mode, both PMOS and NMOS devices are stressed, the proposed structure isolates the PBTI and NBTI degradation during test mode. A methodology of converting any data-path into ring oscillator (DPRO) is also presented. To avoid the performance overhead of attaching monitoring circuitry to functional block, a non-invasive scheme for BTI monitoring is presented for sleep transistor based logic families. Since, BTI is a critical issue for memories, a scheme for BTI monitoring of 6T SRAM cell based memories is also presented. We make use of the concept of a DPRO and show how a memory system can be made to oscillate in test mode. The frequency of oscillation is a function of the devices in the cell. After validation of the proposed schemes using extensive simulations, we have also validated the results on silicon. We also introduce the concept of wearout mitigation at the compiler level. Using an example of a register file, we present a preemptive method of wearout mitigation using a compiler directed scheme.

No description available.

abstract: Negative bias temperature instability (NBTI) and channel hot carrier (CHC) are important reliability issues impacting analog circuit performance and lifetime. Compact reliability models and efficient simulation methods are essential for circuit level reliability prediction. This work proposes a set of compact models of NBTI and CHC effects for analog and mixed-signal circuit, and a direct prediction method which is different from conventional simulation methods. This method is applied in circuit benchmarks and evaluated. This work helps with improving efficiency and accuracy of circuit aging prediction. / Dissertation/Thesis / M.S. Electrical Engineering 2011

L'auteur n'a pas fourni de résumé en français. / Integrated circuits evolution is driven by the trend of increasing operating frequencies and downscaling of the device size, while embedding more and more complex functionalities in a single chip. However, the continuation of the device-scaling race generates a number of technology challenges. For instance, the downscaling of transistor channel lengths induce short-channel effects (drain-induced barrier lowering and punch-through phenomena); high electric field in the devices tend to increase Hot electron effect (or Hot Carrier) and Oxide Dielectric Breakdown; higher temperatures in IC products generates an increase of the Negative Bias Temperature Instability (NBTI) effect on pMOS devices. Today, it is considered that the above reliability mechanisms are ones of the main causes of circuit degradation performance in the field. This dissertation will address the Hot Carrier (HC) and NBTI impacts on CMOS product electrical performances. A CAD bottom-up approach will be proposed and analyzed, based on the Design–in Reliability (DiR) methodology. With this purpose, a detailed analysis of the NBTI and the HC behaviours and their impact at different abstraction level is provided throughout this thesis. First, a physical framework presenting the NBTI and the HC mechanisms is given, focusing on electrical parameters weakening of nMOS and pMOS transistors. Moreover, the main analytical HC and NBTI degradation models are treated in details. In the second part, the delay degradation of digital standard cells due to NBTI, HCI is shown; an in-depth electrical CAD analysis illustrates the combined effects of design parameters and HCI/NBTI on the timing performance of standard cells. Additionally, a gate level approach is developed, in which HC and NBTI mechanisms are individually addressed. The consequences of the degradation at system level are presented in the third part of the thesis. With this objective, data extracted from silicon measures are compared against CAD estimations on two complexes IPs fabricated on STCMOS 45nm technologies. It is expected that the findings of this thesis highly contribute to the understanding of the NBTI and HC reliability wearout mechanisms at the system level.STAR

Degradation of transistor parameter values due to Negative Bias Temperature Instability (NBTI) has emerged as a major reliability problem in current and future technology generations. NBTI Aging of a Static Random Access Memory (SRAM) cell leads to a lower noise margin, thereby increasing the failure rate. The register file, which consists of an array of SRAM cells, can suffer from data loss, leading to a system failure. In this work, we study the source of NBTI stress in an architecture and physical register file. Based on our study, we modified the register file structure to reduce the NBTI degradation and improve the overall system reliability. Having evaluated new register file structures, we find that our techniques substantially improve reliability of the register files. The new register files have small overhead, while in some cases they provide saving in area and power.