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With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.

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Copper-organonitrogen complexes are studied by threshold photoionization and zero electron kinetic energy photoelectron spectroscopy. These complexes are prepared in pulsed laser vaporization supersonic molecular beams. Adiabatic ionization energies of the neutral species and vibrational frequencies of the neutral and ionic complexes were measured. Metal-ligand bond dissociation energies were obtained from the theoretical calculations or the experiments. More importantly, by combining the spectroscopic measurements, quantum chemical calculations, and spectral simulations, metal-ligand bonding structures are determined for copper complexes of diamines, pyridine, diazines, aminopyridines, polypyridines, and imidazole. The Cu-ethylenediamine, -(1,3-propanediamine), and -(1,4-butenediamine) complexes have been determined to be in a hydrogen-bond stabilized monodentate configuration. However, Cu atom binds to both two nitrogens in the methyl-substituted ethylenediamines. The change of the Cu binding from the monodentate to the bidentate mode arises from the competition between copper coordination and hydrogen bonding. Although pyridine, diazines, and imidazole molecules can function as a s-donor through the nitrogen atom, a p-acceptor or p-donor through six-membered or five-membered aromatic ring, only the s bonding mode is predicted by the theory and identified by the ZEKE spectroscopy. For aminopyridine molecules, s bonding through the sp2 or sp3 hybrid electron lone pair and p bonding through the pyridine ring are possible. Yet, the s bonding through the sp2 electron donation is calculated to be the strongest, and the Cuaminopyridine complexes formed by such bonding mechanism are identified by the experiments. Moreover, monodentate Cu-(4,4'-bipyridine), bidentate Cu-(2,2'-bipyridine) and Cu-(1,10-phenanthroline), and tridentate Cu-(2,2':6',2?-terpyridine) are established to be the most stable structure and are observed by experiments. It is surprising to find that the tridendate planar structure of Cu-(2,2':6',2?-terpyridine) changes to a twisted Cs structure upon ionization.

The phosphine crown ether, 16-(4'diphenylphosphinophenyl)-1,4,7,10,13-pentaoxa-16azacyclooctadecane (III), was synthesized using a reaction scheme beginning with n-phenyldiethanolamine and the dichloride of tetraethylene glycol, with an overall yield of 4%. Platinum and Palladium complexes of the ligand, of the form MC12L2, were synthesized as well. 13C NMR and picrate extraction data indicate III and IV (the crown-5 analog) both moderately bind sodium (14%, 15%) and potassium ions (17%, 28%). Compound V (a crown-5, triphenylphosphine-based ligand) will bind both sodium and potassium ions as well (18%, 6%). When IV is complexed to nickel carbonyl (Ni(CO)3), the addition of sodium and potassium ions cause the Al carbonyl stretching frequency to increase slightly (0.3 cm-1, 0.2 cm 1). For comparison, the addition of a proton causes the A1 carbonyl stretching frequency to increase 5.2 cm-1. However, the shift in the A1 carbonyl stretching frequency upon the addition of sodium or potassium ions indicates that ion binding by the crown ether is communicated to the phosphorus and finally to the carbonyl groups.Ball State UniversityMuncie, IN 47306 / Department of Chemistry

In this thesis, we are making a new approach to fabricate silicon on insulator (SOI). By replacing the buried silicon dioxide and the silicon handling wafer with silicon carbide through hydrophilic wafer bonding, we have achieved silicon on crystalline silicon carbide for the first time and silicon on polycrystalline silicon carbide substrates at 150 mm wafer size. The conditions for the wafer bonding are studied and the surface and bond interface are characterized. Stress free and interfacial defect free hybrid wafer bonding has been achieved. The thermally unfavourable interfacial oxide that originates from the hydrophilic treatment has been removed through high temperature annealing, denoted as Ox-away. Based on the experimental observations, a model to explain the dynamics of this process has been proposed. Ox-away together with spheroidization are found to be the responsible theories for the behaviour. The activation energy for this process is estimated as 6.4 eV. Wafer bonding of Si and polycrystalline SiC has been realised by an intermediate layer of amorphous Si. This layer recrystallizes to some extent during heat treatment. Electronic and thermal testing structures have been fabricated on the 150 mm silicon on polycrystalline silicon carbide hybrid substrate and on the SOI reference substrate. It is shown that our hybrid substrates have similar or improved electrical performance and 2.5 times better thermal conductivity than their SOI counterpart. 2D simulations together with the experimental measurements have been carried out to extract the thermal conductivity of polycrystalline silicon carbide as κpSiC = 2.7 WK-1cm-1. The realised Si-on-SiC hybrid wafer has been shown to be thermally and electrically superior to conventional SOI and opens up for hybrid integration of silicon and wide band gap material as SiC and GaN.

Wire bonding is the process of creating interconnects between the circuitry on a microchip and PCB boards or substrates so that the microchip can interact with the outside world. The materials and techniques used in this bonding process can cause a wide variation in bond quality, so wire bond reliability testing is very important in determining the quality and longevity of wire bonds. Due to the fact that microchips are encased in protective resins after bonding and their substrates attached to the larger device as a whole, once any single wire bond fails then it could jeapordize the entire device as the wire bonds cannot be individually replaced or fixed. Current methods of reliability testing are lengthy and often destroy the entire sample in the process of evaluation, so the availability of novel non-destructive, real-time monitoring methods as well as accelerated aging could reduce costs and provide realistically timed tests of novel wire bond materials which do not form Intermetallic compounds (IMCs) as rapidly as Au wire on Al substrates. In this thesis, five new chip designs for use in wire bond reliability testing are reported, focusing on the first joint made in a wire bond, called the ball bond. These chips are scaled either to test up to 55 test bonds simultaneously or just one at a time, introducing different requirements for microchip infrastructure capabilities, such as on-chip sensing/data bus, multiplexer, and switches able to operate under High Temperature Storage (HTS) which ranges from temperatures of 150-220 ??C. There are different heating requirements for each of these microchips, needing to be heated externally or containing on-chip microheaters to heat only the ball bond under test, and not the rest of the microchip or surrounding I/O pads. Of the five chip designs, sample chips were produced by an external company. Experimental studies were then carried out with two of these chip designs. They were specifically made to test novel methods of determining ball bond reliability using in-situ, non-destructive sensing, in real-time, while the ball bond undergoes thermal aging. Pad resistance as an analysis tool for ball bond reliability is proposed in this thesis as a new way of evaluating ball bond quality and allows for the testing of electrical connection without the need for specialized measurement probes or difficult bonding processes that contact resistance measurements require. Results are reported for pad resistance measurements of a ball bond under very high temperature storage (VHTS) at 250 ??C, a temperature exceeding typical HTS ranges to accelerate aging. Pad resistance measurements are taken using the four-wire measurement method from each corner of the bond pad, while reversing current direction every measurement to remove thermo-electric effects, and then calculating the average square resistance of the pad from this value. The test ball bond is aged using a novel on-chip microheater which is a N+ doped Si resistive heater located directly underneath the bond pad, and can achieve temperatures up to 300 ??C while not aging any of the I/O pads surrounding it, which are located ~180 ??m away. A 50 ??? resistor is placed 60 ??m away from the heater to monitor the temperature. The use of a microheater allows the aging of novel wire types at temperatures much higher than those permitted for microchip operation while thermally isolating the test bond from the sensing and power bonds, which do not need to be aged. Higher temperatures allow the aging process to be sped up considerably. The microheater is programmatically cycled between 250 ??C (for 45 min) and 25 ??C (for 15 min) for up to 200 h or until the pad resistance measurements fail due breakdown of the bonding pad. Intermetallic compounds forming between the ball bond and the pad first become visible after a few hours, and then the pad becomes almost completely consumed after a day. The pad resistance is measured every few seconds while the sample is at room temperature, and the increase in pad resistance agrees with the fact that Au/Al IMC products are known to have much higher resistance than both pure Au or Al. Also discussed are some aging results of Au wires and Pd coated Cu (PCC) wires bonded to Al bonding pads and aged at a temperature of 200 ??C in an oven for 670 h. The oven aged Au ball bonds also saw IMC formation on the surface of the bonding pad, much like the microheater tests. The PCC ball bonds became heavily oxidized due to lack of Pd on the surface of the ball, the wire portions did not oxidize much. In conclusion, the new structures have been demonstrated to age ball bonds faster than with conventional methods while obtaining non-destructive data. Specifically, the new microheater ages a test bond at an accelerated rate without having an observable effect on the I/O connections used to monitor the test bond. Pad resistance measurements correlate to the aging of the test bond and ensure the electrical integrity of the joint is checked.

Oxide dispersion strengthened (ODS) alloys have been developed with unique mechanical properties. However, in order to achieve commercial application an appropriate joining process is necessary which minimizes disruption to the alloy microstructure. Transient liquid phase (TLP) bonding is a promising joining method, but previous work has shown that the segregation of dispersoids within the joint region results in bonds with poor mechanical strengths. This research work was undertaken to further explore particulate segregation at the joint region when TLP bonding and to develop bonding techniques to prevent it. A Ni-Cr-Fe-Si-B interlayer was used to bond an alloy MA 758. The effects of parent alloy grain size, bonding temperature, and external pressure on the TLP bonding process were investigated. Three melting stages were identified for the interlayer, and the bonding temperature was chosen so that the interlayer was in the semi-solid state during bonding. This novel bonding mechanism is described and applied to counteract the segregation of Y203 dispersoids. The grain size of the parent alloy does not alter the particulate segregation behaviour. It is concluded that a low bonding temperature with moderate pressure applied during bonding is preferable for producing bonds with less disruption to the microstructures of the parent alloy. Joint shear tests revealed that a near parent alloy strength can be achieved. This study also shed some light on choosing the right bonding parameters suitable for joining the complicated alloy systems. A Ni-P interlayer was also used to bond the ODS alloy. Microstructural examination indicated that a thin joint width and less disruption to the parent grain structure were achieved when bonding the alloy in the fine grain state. The time for isothermal solidification was found to be shorter when compared with bonds made with the parent alloy in the recrystallized state. All these observations were attributed to the greater diffusivity of P along the grain boundaries than that of the bulk material. A high Cr content within the parent alloy changes the mechanism of the bonding process. The diffusion of Cr into the liquid interlayer has the effect of raising the solidus temperature, which not only accelerates the isothermal solidification process, but also reduces the extent of parent alloy dissolution.