Multimedia applications pose new challenges to computer architecture. Their tremendous communication demands severely burden the interconnect between functional units. This dissertation addresses to efficiently transport operands among computational and storage components. It provides architectural enhancements that enable the high bandwidth, low latency communication. This research analyzes multimedia workloads to characterize the communication patterns that occur in the execution of standard multimedia benchmarks. This empirical analysis indicates that most operands exhibit strong locality, enabling several optimizations of transport mechanisms. This empirical study shows that an eight-entry local buffer with approximate information on operand lifetime is sufficient to suppress 81% of operand writes. In addition, chaining selected pairs of FUs based on producer-consumer information allows 50% of reads to be accessed through the shortest path. These results guide the design of two efficient operand transport mechanisms: a traffic-driven bypass network and a dynamic instruction clustering. The traffic-driven bypass network is designed using a novel, systematic design customization process for wide-issue architectures. It is driven by a technology model-based evaluation methodology, resulting in a low cost, high performance bypass network for multimedia applications. This technique places microarchitectural components exploiting the communication patterns, reorganizes bypass paths based on the traffic rate, and maps inter-instruction communication on the local paths. The reduction in transport latency combined with a faster clock cycle achieves an instruction throughput gain of 2.9x over the broadcast bypass network at 45nm. In addition, the throughput gain over a typical clustered architecture is 1.3x. Dynamic instruction clustering groups dependent instructions into clusters during instruction execution, performs operand transport pattern analysis, and maps the clustered instructions to a cluster execution unit. Two execution unit implementations are explored: network ALUs and a dynamically-scheduled SIMD PE array. In the network ALUs, intermediate values are propagated among ALUs without distribution through global bypass buses. The reduction in operand transport latency results in a 35% IPC speedup over a conventional ILP processor. The dynamically-scheduled SIMD PE array supports DLP processing of the innermost loops in image processing applications. Data-parallel operations combined with localized operand communication produce an IPC speedup of 2.59x over a 16-way, four-clustered microarchitecture.

The first topic of this thesis is a mixed radix-16/8/4/2 64b/32b integer divider which uses a variety of techniques, including operand scaling, table partitioning, and table sharing, to increase performance without paying the cost of increasing complexity. The second topic is a noise immune address transition detector¡]ATD¡^circuit. We employ a simple feedback loop to stabilize the generated CS¡]chip select¡^signal and two delay cells to dynamically adjust the width of the CS strobe.

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Purpose – This article seeks to advance a novel service network perspective, based on the service-dominant logic, designated as service-dominant networks (SDN). Design/methodology/approach – Service-dominant logic components serve to build and describe SDN. Specifically, resources and actors are key components, combined with activities and the process by which they become resources. A case study details the features of SDNs. Findings – Service-dominant networks exhibit unique, previously unaddressed features. According to the service-dominant logic, components only become resources when they are integrated; thus, they disappear as resources after their integration, which means SDNs are fugacious: they (be-)come and go. In addition, SDNs comprise one or more main intended activities that explain their existence, though these intended activities do not necessarily initiate any particular SDN. Rather, other critical incidents can initiate SDNs. Research limitations/implications – The features of SDNs proposed in this article have not been a focus of prior research. In particular, the dynamics and fugaciousness of SDNs are challenges for research and management. Originality/value – This article offers the first proposal of a novel, service-dominant network perspective. In a very general and abstract form, it identifies the features of SDNs.

Thesis (Ph.D. (Criminology)) -- University of Limpopo, 2015 / The research concerned with the aim of this study, was to assess the appli-cation of intelligence-driven investigation in combating organised motor vehicle theft. The strategic intelligence plan, information sharing and understanding of or-ganised vehicle theft, are some of approaches which will assist in dealing with the challenge of the illegal sale of vehicles and vehicle parts. There is indeed a need to address police corruption, if the battle against vehicle theft is to be realised. The objectives of this study were the following: to explain the strategic intelli-gence plan for investigating motor vehicle theft; to evaluate whether investiga-tions of organised motor vehicle theft in Thohoyandou cluster are intelligence-driven; to assess if the cluster uses intelligence offender profiling in investi-gations; to explore how intelligence-driven investigation assists in information sharing; and, to make recommendations for the improvement of intelligence-driven vehicle theft investigation. The researcher wanted to apply new research knowledge, in order to develop good practice in the field. This has been done by recommending new proced-ures to enhance performance and to improve the ways and means of combating organised vehicle theft. KEY TERMS Intelligence-driven investigation; strategic intelligence; intelligence cycle; crime investigations; modus operandi; offender profiling; organised crime; systems theory; motor vehicle theft; information sharing.

Purpose – This article seeks to advance a novel service network perspective, based on the service-dominant logic, designated as service-dominant networks (SDN). Design/methodology/approach – Service-dominant logic components serve to build and describe SDN. Specifically, resources and actors are key components, combined with activities and the process by which they become resources. A case study details the features of SDNs. Findings – Service-dominant networks exhibit unique, previously unaddressed features. According to the service-dominant logic, components only become resources when they are integrated; thus, they disappear as resources after their integration, which means SDNs are fugacious: they (be-)come and go. In addition, SDNs comprise one or more main intended activities that explain their existence, though these intended activities do not necessarily initiate any particular SDN. Rather, other critical incidents can initiate SDNs. Research limitations/implications – The features of SDNs proposed in this article have not been a focus of prior research. In particular, the dynamics and fugaciousness of SDNs are challenges for research and management. Originality/value – This article offers the first proposal of a novel, service-dominant network perspective. In a very general and abstract form, it identifies the features of SDNs.

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<p>Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well.</p><p>In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources.</p><p>In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations.</p><p>The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs.</p><p>Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.</p>

Multiplications occur frequently in digital signal processing systems, communication systems, and other application specific integrated circuits. Multipliers, being relatively complex units, are deciding factors to the overall speed, area, and power consumption of digital computers. The diversity of application areas for multipliers and the ubiquity of multiplication in digital systems exhibit a variety of requirements for speed, area, power consumption, and other specifications. Traditionally, speed, area, and hardware resources have been the major design factors and concerns in digital design. However, the design paradigm shift over the past decade has entered dynamic power and static power into play as well. In many situations, the overall performance of a system is decided by the speed of its multiplier. In this thesis, parallel multipliers are addressed because of their speed superiority. Parallel multipliers are combinational circuits and can be subject to any standard combinational logic optimization. However, the complex structure of the multipliers imposes a number of difficulties for the electronic design automation (EDA) tools, as they simply cannot consider the multipliers as a whole; i.e., EDA tools have to limit the optimizations to a small portion of the circuit and perform logic optimizations. On the other hand, multipliers are arithmetic circuits and considering arithmetic relations in the structure of multipliers can be extremely useful and can result in better optimization results. The different structures obtained using the different arithmetically equivalent solutions, have the same functionality but exhibit different temporal and physical behavior. The arithmetic equivalencies are used earlier mainly to optimize for area, speed and hardware resources. In this thesis a design methodology is proposed for reducing dynamic and static power dissipation in parallel multiplier partial product reduction tree. Basically, using the information about the input pattern that is going to be applied to the multiplier (such as static probabilities and spatiotemporal correlations), the reduction tree is optimized. The optimization is obtained by selecting the power efficient configurations by searching among the permutations of partial products for each reduction stage. Probabilistic power estimation methods are introduced for leakage and dynamic power estimations. These estimations are used to lead the optimizers to minimum power consumption. Optimization methods, utilizing the arithmetic equivalencies in the partial product reduction trees, are proposed in order to reduce the dynamic power, static power, or total power which is a combination of dynamic and static power. The energy saving is achieved without any noticeable area or speed overhead compared to random reduction trees. The optimization algorithms are extended to include spatiotemporal correlations between primary inputs. As another extension to the optimization algorithms, the cost function is considered as a weighted sum of dynamic power and static power. This can be extended further to contain speed merits and interconnection power. Through a number of experiments the effectiveness of the optimization methods are shown. The average number of transitions obtained from simulation is reduced significantly (up to 35% in some cases) using the proposed optimizations. The proposed methods are in general applicable on arbitrary multi-operand adder trees. As an example, the optimization is applied to the summation tree of a class of elementary function generators which is implemented using summation of weighted bit-products. Accurate transistor-level power estimations show up to 25% reduction in dynamic power compared to the original designs. Power estimation is an important step of the optimization algorithm. A probabilistic gate-level power estimator is developed which uses a novel set of simple waveforms as its kernel. The transition density of each circuit node is estimated. This power estimator allows to utilize a global glitch filtering technique that can model the removal of glitches in more detail. It produces error free estimates for tree structured circuits. For circuits with reconvergent fanout, experimental results using the ISCAS85 benchmarks show that this method generally provides significantly better estimates of the transition density compared to previous techniques.