No description available.

This dissertation explores a few techniques to realize a low-cost monolithic fiber-optic receiver with large-area photo detectors in advanced CMOS processes that could potentially support multi-gigabit digital data across 10 to 20 meters plastic optical fibers (POF). The first techniques investigated in this dissertation are the use of an external pseudo-differential photo detector chip to reduce the impact of the inductive parasitics, and the use of a cross-coupled regulated-cascode (CC-RGC) buffer to relieve the DC voltage headroom issues found in conventional regulated-cascode (RGC) buffers in technologies with low power supply voltages. The second technique investigated in this thesis is the super-Gm transimpedance amplifier (SGM-TIA) that can be used to produce a very small input impedance in order to drive a very large parasitic capacitance exhibited by an integrated photo detector in advanced CMOS processes. The third technique investigated is a linear equalizer with multiple shunt-shunt feedbacks that can be utilized to produce a slowly-rising peaking response in order to compensate for the frequency-dependent losses exhibited by the integrated NW/P-sub photo detector. Two prototype POF receiver test chips have been implemented in TSMC’s 65 nm CMOS processes and non-return-to-zero optical data transmissions have been demonstrated at data rates up to 3.125 Gbps and 4.25 Gbps, respectively, with a 2.5 Gbps grade 670 nm vertical-cavity surface-emitting laser based electro-optical transmitter.

This dissertation explores a few techniques to realize a low-cost monolithic fiber-optic receiver with large-area photo detectors in advanced CMOS processes that could potentially support multi-gigabit digital data across 10 to 20 meters plastic optical fibers (POF). The first techniques investigated in this dissertation are the use of an external pseudo-differential photo detector chip to reduce the impact of the inductive parasitics, and the use of a cross-coupled regulated-cascode (CC-RGC) buffer to relieve the DC voltage headroom issues found in conventional regulated-cascode (RGC) buffers in technologies with low power supply voltages. The second technique investigated in this thesis is the super-Gm transimpedance amplifier (SGM-TIA) that can be used to produce a very small input impedance in order to drive a very large parasitic capacitance exhibited by an integrated photo detector in advanced CMOS processes. The third technique investigated is a linear equalizer with multiple shunt-shunt feedbacks that can be utilized to produce a slowly-rising peaking response in order to compensate for the frequency-dependent losses exhibited by the integrated NW/P-sub photo detector. Two prototype POF receiver test chips have been implemented in TSMC’s 65 nm CMOS processes and non-return-to-zero optical data transmissions have been demonstrated at data rates up to 3.125 Gbps and 4.25 Gbps, respectively, with a 2.5 Gbps grade 670 nm vertical-cavity surface-emitting laser based electro-optical transmitter.

The objective of this work was to integrate an optical receiver in a modern standard technology in a form amenable to multiple lanes. To accomplish this goal, a photodiode was integrated with the receiver in a standard 90nm CMOS process and the nominal process voltage of 1.2V was not exceeded. Two optical lanes were integrated on chip with a pitch compatible with existing industry photodiode arrays. This work uses a non-SML photodiode to increase optical responsivity to 0.141A/W, almost 3 times higher than values typically reported for SML photodiodes. This receiver is the first integrated optical receiver reported in a standard CMOS technology with a feature size smaller than 0.13μm, which is necessary for the eventual integration of optical receivers with modern digital processing blocks on a single die. The traditional analog equalizer used in most integrated optical receivers is replaced with a high-pass filter and hysteresis latch for equalization. The receiver occupies a core area of 0.197mm2 and has an optical sensitivity of -3.7dBm at a 2Gbps data rate, while consuming 46.3mW.

The objective of this work was to integrate an optical receiver in a modern standard technology in a form amenable to multiple lanes. To accomplish this goal, a photodiode was integrated with the receiver in a standard 90nm CMOS process and the nominal process voltage of 1.2V was not exceeded. Two optical lanes were integrated on chip with a pitch compatible with existing industry photodiode arrays. This work uses a non-SML photodiode to increase optical responsivity to 0.141A/W, almost 3 times higher than values typically reported for SML photodiodes. This receiver is the first integrated optical receiver reported in a standard CMOS technology with a feature size smaller than 0.13μm, which is necessary for the eventual integration of optical receivers with modern digital processing blocks on a single die. The traditional analog equalizer used in most integrated optical receivers is replaced with a high-pass filter and hysteresis latch for equalization. The receiver occupies a core area of 0.197mm2 and has an optical sensitivity of -3.7dBm at a 2Gbps data rate, while consuming 46.3mW.

No description available.

This thesis examines the design of high speed transimpedance amplifiers (TIAs) in low cost complimentary metal oxide semiconductor (CMOS) technology. Due to aggressive scaling, CMOS has become an attractive technology for high speed analog circuits. Besides the cost advantage, CMOS offers the potential for higher levels of integration since the analog circuits can be integrated with digital electronics on the same substrate. A 2.5 Gbps transimpedance amplifier fabricated using 0.18 um CMOS technology is presented. The TIA uses a shunt-shunt feedback topology with a cascode gain stage. Measurements of the transimpedance gain, group delay, and common mode rejection ratio are presented for the TIA and show a good match to simulated results. The noise of the TIA was characterized by measuring the noise parameters of the TIA. The noise parameters are then used to determine the input referred noise current spectral density. A 10 Gbps transimpedance amplifier fabricated using 0.18 um CMOS technology is also presented. This TIA uses a shunt-shunt feedback topology with a common source gain stage. In order to achieve the required bandwidth, the TIA uses a bandwidth extension technique called shunt-series inductive peaking. A discussion of the different methods of bandwidth extension using inductive peaking is included, and the optimal configurations for maximally flat responses are shown for shunt inductive peaking,series inductive peaking, and shunt-series inductive peaking. The TIA circuit topology is optimized using a novel noise analysis that uses a high frequency noise model for the transistor. The optimum transistor size and bias current are determined to minimize the amplifier noise. Unfortunately differential measured results are not available due to a stability problem in the amplifier. The cause of this instability is further explored and modifications to solve the problem are discussed. Single-ended results are presented and show reasonable agreement with simulated results. Differences in the results are attributed to poor modelling of the on-chip spiral inductors. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2007-07-16 13:34:41.46

Este informe técnico propone el diseño de un bloque llamado Amplificador Limitador que se encuentra en los equipos que trabajan con fibra óptica o con altas tasas de transmision de datos y que estan integrados en una pastilla de silicio. El objetivo principal es aumentar el ancho de banda de un Amplificador Limitador mediante la aplicación de la técnica Inductive Peaking para lograr velocidades que corresponden a una portadora óptica OC-192 equivalente a 10 Gbps bajo el estándar SONET. Haciendo uso de tecnología CMOS con transistores de 130 nm de ancho de canal. A su vez se propone disminuir el consumo de potencia y el área ocupada en la pastilla de Silicio utilizando inductores activos y la eliminación de los capacitores de desacople DC entre etapas. Los resultados finales Post Layout demuestran que es posible extender el ancho de banda con las técnicas mencionadas anteriormente, reducir el consumo total y el área ocupada en la pastilla de Silicio y cumplir con las especificaciones técnicas requeridas. This technical report proposes the design of a block called Limiting Amplifier which is found in equipment that works with optical fiber or with high rates of data transmission and that are integrated in a silicon wafer. The main objective is to increase the bandwidth of a limiter amplifier by applying the Inductive Peaking technique to achieve speeds that correspond to an OC-192 optical carrier equivalent to 10 Gbps under the SONET standard, making use of CMOS technology with 130 nm channel width transistors. At the same time, it is proposed to reduce the power consumption and the area occupied in the chip using active inductors and the elimination of DC decoupling capacitors between stages. The final results of Post Layout show that it is possible to extend the bandwidth with the techniques mentioned above, reducing the total consumption and the area occupied in the silicon pellet and accomplishing with the required technical specifications.

<p> Due to the high cost, telephone and cable television companies can only justify installing fiber optical networks to remote sites which serve up to a few hundred customers. For customers located at variable distances from the transmitting station, they will receive signals at different strengths. The signal stability and system reliability of FTTH network affected largely by the distance. We propose an effective solution for the enhancement of signal stability of FTTH network, which uses a semiconductor optical amplifier (SOA) coupled with an optical receiver.</p> <p> Before the signal reaches the optical receiver at the user end, signal strength is automatically adjusted through a semiconductor optical amplifier (SOA). Due to the special saturation property of SOA, the output optical signal will have very small fluctuation regardless the input optical signal power, the signal stability of FTTH network will be improved significantly. A set of simplified governing equations of SOA has been proposed and the corresponding numerical solver has been implemented. Although the main focus is primarily the SOA, a simplified optical receiver is also simulated, which comprises a PIN photodetector and a low pass filter (LPF). All simulations have been carried out in the time-domain with the frequency domain low pass filter modeled by a digital filter.</p> / Thesis / Master of Applied Science (MASc)

Abstract The aim of this thesis was to develop time-to-digital converters (TDC) for the integrated receiver of a pulsed time-of-flight (TOF) laser rangefinder aiming at cm-level accuracy over an input range of 10 m&#160;–&#160;15 m. A simple structure, a high integration level and low power consumption are the desired features for such a TDC. From the pulsed TOF laser rangefinder point of view an integrated receiver consisting of both the TDC and the receiver channel on the same die offers the possibility of manufacturing these laser rangefinders with a high integration level and at a low price to fulfil the needs of mass industrial markets. The heart of the TDC is a CMOS ring oscillator, the clock frequency of which is used to calculate the full clock cycles between timing signals, the positions of the timing signals inside the clock period being determined by storing the state of the phase of the ring oscillator for each timing signal. This will improve the resolution of the TDC. Also, additional delay lines are used to generate multiple timing signals, each having a time difference of a fraction of that of the ring oscillator. This will further improve the resolution of the whole TDC. To achieve stable results regardless of temperature and supply voltage variations, the TDC is locked to an on-chip reference voltage, or the resolution of the TDC is calibrated before the actual time interval measurement. The systematic walk error in the receiver channel caused by amplitude variation in the received pulse is compensated for by the TDC measuring the slew rate of the received pulse. This time domain compensation method is not affected by the low supply voltage range of modern CMOS technologies. Three TDC prototypes were tested. A single-shot precision standard deviation of 16 ps (2.4&#160;mm) and a power consumption of 5.3&#160;mW/channel were achieved at best over an input range of 100 ns (15 m). The temperature drifts of an on-chip voltage reference-locked TDC and a TDC based on the calibration method were 90 ppm/&#176;C and 0.27 ps/&#176;C, respectively. The results also showed that a pulsed TOF laser rangefinder with cm-level accuracy over a 0&#160;–&#160;15 m input range can be realized using the integrated receiver with the time domain walk error compensation described here. / Tiivistelmä Väitöskirjatyön tavoitteena oli kehittää aika-digitaalimuunninrakenteita valopulssin kulkuajan mittaukseen perustuvan lasertutkan integroituun vastaanottimeen. Tavoitteena oli saavuttaa senttimetriluokan tarkkuus 10&#160;m&#160;–&#160;15&#160;m mittausalueella koko lasertutkan osalta. Aika-digitaalimuuntimelta vaaditaan yksinkertaista rakennetta, korkeaa integroimisastetta ja matalaa tehonkulutusta. Integroitu vastaanotin sisältää sekä aika-digitaalimuuntimen että vastaanotinkanavan ja tarjoaa mahdollisuuden korkeasti integroidun lasertutkan valmistukseen halvalla teollisuuden massamarkkinoiden tarpeisiin. Aika-digitaalimuuntimen ytimenä toimii monivaiheinen CMOS-rengasoskillaattori. Aika-digitaalimuunnos perustuu rengasoskillaattorin täysien kellojaksojen laskentaan laskurilla ajoitussignaalien välillä. Lisäksi rengasoskillaatorin jokaisesta vaiheesta otetaan näyte ajoitussignaaleilla niiden paikkojen määrittämiseksi kellojakson sisällä, jolloin aika-digitaalimuuntimen erottelutarkkuutta saadaan parannettua. Erottelutarkkuutta parannetaan lisää viivästämällä ajoitussignaaleja viive-elementeillä ja muodostamalla näin useita erillisiä ajoitussignaaleja, joiden väliset viive-erot ovat murto-osa rengasoskillaattorin viive-elementin viiveestä. Aika-digitaalimuunnin stabiloidaan käyttöjännite- ja lämpötilavaihteluja vastaan lukitsemalla se integroidun piirin sisäiseen jännitereferenssiin, tai sen erottelutarkkuus määritetään ennen varsinaista aikavälinmittausta erillisellä kalibrointimittauksella. Vastaanotetun valopulssin amplitudivaihtelun aiheuttama systemaattinen ajoitusvirhe integroidussa vastaanotinkanavassa kompensoidaan mittaamalla vastaanotetun valopulssin nousunopeus aika-digitaalimuuntimella. Tällainen aikatasoon perustuva kompensointimetodi on myös suorituskykyinen nykyisissä matalakäyttöjännitteisissä CMOS-teknologioissa. Työssä valmistettiin ja testattiin kolme aika-digitaalimuunninprototyyppiä. Muuntimien kertamittaustarkkuuden keskihajonta oli parhaimmillaan 16 ps (2,4 mm) ja tehonkulutus alle 5,3&#160;mW/kanava mittausetäisyyden olessa alle 100 ns (15 m). Sisäiseen jännitereferenssiin lukitun aika-digitaalimuuntimen lämpötilariippuvuudeksi mitattiin 90 ppm/&#176;C ja kalibrointimenetelmällä saavutettiin 0,27 ps/&#176;C lämpötilariipuvuus. Työssä saavutetut tulokset osoittavat lisäksi, että valopulssin kulkuajan mittaukseen perustuvalla lasertutkalla on saavutettavissa senttimetriluokan tarkkuus 0&#160;–&#160;15 m mittausalueella käyttämällä tässä työssä esitettyä integroitua vastaanotinta ja aikatason ajoitusvirhekompensointia.