Performance evaluation continues to play an important role in network research. Two types of research efforts related to network performance evaluation are particularly noteworthy: (1) using performance evaluation to understand specific problems and to design better solutions, and (2) designing efficient performance evaluation methodologies. This thesis addresses several performance evaluation challenges, encompassing both categories of effort listed above, in building high-performance TCP-based network services in the context of overlay routing and peer-to-peer systems. With respect to the first type of research effort, this thesis addresses two issues related to the design of TCP-based network services: 1. Prediction of large transfer TCP throughput: Predicting the TCP throughput attainable on given paths is used for applications such as route selection in overlay routing. Based on a systematic measurement study, we evaluate the accuracy of two categories of TCP throughput prediction techniques. We then analyze the factors that affect the accuracy of each. 2. Congestion control and message loss in Gnutella peer-to-peer networks: We evaluate the congestion control mechanisms and message loss behavior in a real-world overlay network, the Gnutella system. The challenges for congestion control in such a network are analyzed, as are the design tradeoffs of alternative mechanisms. In order to study systems such as the above with details of the network, we build a scalable, extensible and portable packet-level simulator of peer-to-peer systems. The second part of the thesis, representing the second type of effort above, proposes two techniques to improve network simulation by exploiting the detailed knowledge of TCP: 1. Speed up network simulation by exploiting TCP steady-state predictability: We develop a technique that uses prediction to accurately summarize a series of packet events and, therefore, to save on processing cost while maintaining fidelity. Our technique integrates well with packet-level simulations and is more faithful in several respects than previous optimization techniques. 2. TCP workload generation under link load constraints: We develop an algorithm that generates traffic for a specific network configuration such that realistic and specific load conditions are obtained on user-specified links. At the same time, the algorithm minimizes the simulation memory requirement.

<p>This report concerns the implementation of a simulation framework to evaluate an emerging peer-to-peer network topology scheme using 8-point hypercircles, entitled HyperCircle. This topology was proposed in order to alleviate some of the drawbacks of current P2P systems evolving in an uncontrolled manner, such as scalability issues, network overload and long search times. The framework is supposed to be used to evaluate the advantages of this new topology. The framework has been built on top of an existing simulator software solution, the selection of which was an important part of the development. Weighing different variables such as scalability and API usability, the selection fell on OverSim, an open-source discreet-event simulator based on OMNET++.</p><p>After formalizing the protocol for easier implementation, as well as extending it for better performance, implementation followed using C++ with OverSim’s API and simulation library. Implemented as a module (alongside other stock modules providing their own protocols such as Chord and Kademlia), it can be used in OverSim to simulate a user-defined network using one of the simulation routine applications provided (or using a custom application written by the user). For the purposes of this thesis, the standard application KBRTestApp was used; an application sending test messages between randomly selected nodes, while adding and removing nodes at specific time intervals. The adding and removing of nodes can be configured with probability parameters.</p><p>Tentative testing shows that this implementation of the HyperCircle protocol has a certain performance gain over the OverSim implementations of the Chord and Kademlia protocols, measurable in the time it takes a message to get from sender to recipient. Further testing is outside the scope of this thesis.</p>

Significant research has been initiated recently to devise control strategies that could predict and compensate manufacturing errors using so called explicit Stream-of-Variation(SoV) models that relate process parameters in a Multistage Manufacturing Process (MMP) with product quality. This doctoral dissertation addresses several important scientific and engineering problems that will significantly advance the model-based, active control of quality in MMPs. First, we will formally introduce and study the new concept of compensability in MMPs, analogous to the concept of controllability in the traditional control theory. The compensability in an MMP is introduced as the property denoting one’s ability to compensate the errors in quality characteristics of the workpiece, given the allocation and character of measurements and controllable tooling. The notions of “within-station” and “between-station” compensability are also introduced to describe the ability to compensate upstream product errors within a given operation or between arbitrarily selected operations, respectively. The previous research also failed to concurrently utilize the historical and on-line measurements of product key characteristics for active model-based quality control. This dissertation will explore the possibilities of merging the well-known Run-to-Run (RtR) quality control methods with the model-based feed-forward process control methods. The novel method is applied to the problem of control of multi-layer overlay errors in lithography processes in semiconductor manufacturing. In this work, we first devised a multi-layer overlay model to describe the introduction and flow of overlay errors from one layer to the next, which was then used to pursue a unified approach to RtR and feedforward compensation of overlay errors in the wafer. At last, we extended the existing methodologies by considering inaccurately indentified noise characteristics in the underlying error flow model. This is also a very common situation, since noise characteristics are rarely known with absolute accuracy. We formulated the uncertainty in process noise characteristics using Linear Fractional Transformation (LFT) representation and solved the problem by deriving a robust control law that guaranties the product quality even under the worst case scenario of parametric uncertainties. Theoretical results have been evaluated and demonstrated using a linear state-space model of an actual industrial process for automotive cylinder head machining. / text

In the recent years threaded run-to-run (RtR) control algorithms have experienced drawbacks under certain circumstances, one such trait is when applied to high-mix of products such as in Application Specific Integrated Circuits (ASIC) foundries. The variations in the process are a function of the product being manufactured as well as the tool being used. The presence of semiconductor layers increases the number of times the lithography process must be repeated. Successive layers having different patterns must be exposed using different reticles/masks in order to maximize tool utilizations. The objectives of this research are to develop a set of methodologies for evaluation and extension of threaded control applied to overlay. This project defines methods to quantify the efficacy of threaded controls, finds the drawbacks of threaded control under production of high mix of semiconductors and suggests extensions and alternatives to improve threaded control. To evaluate the performance of threaded control, extensive simulations were performed in MATLAB. The effects of noise, disturbances, sampling and delays on the control and estimation performance of threaded controller were studied through these simulations. Based on the results obtained, several ideas to extend threaded control by reducing overall number of threads, by improving thread definitions and combination have been introduced. A unique idea of sampling the measurements dynamically based on the estimation accuracy is also presented. Future work includes implementing the extensions to threaded control suggested in this work in real production data and comparing the results without the use of those methods. Future work also includes building new alternatives to threaded control. / text

As nanometer Very Large Scale Integration (VLSI) demands more transistor density to fabricate multi-cores and memory blocks in a limited die size, many researches have been performed to keep Moore's Low in two different ways: 2D geometric shrinking and 3D vertical wafer stacking. For the geometric shrinking, nano patterning with 193nm lithography equipment is one of the most fundamental challenges beyond 22nm while the next-generation lithography, such as Extreme Ultra-Violet (EUV) lithography still faces tremendous challenges for volume production in the near future. As a practical solution, Double Patterning Lithography (DPL) has become a leading candidate for sub-20nm lithography process. Another approach for multi-core integration is 3D wafer stacking with Through Silicon Via (TSV). Computer-Aided-Design (CAD) approaches to enable robust DPL and TSV technology are the main focus of this dissertation. DPL poses new challenges for overlay and layout decomposition. Therefore, overlay induced variation modeling and efficient decomposition for better manufacturability are in great demand. Since the variation of metal space caused by overlay results in coupling capacitance variation, we first model metal spacing variation with individual overlay sources. Then, all overlay sources are considered to determine the worst timing with coupling capacitance variation. Non-parallel pattern caused by overlay is converted to parallel one with equivalent spacing having the same delay to be applicable of a traditional RC extraction flow. Our experiments show that the delay variation due to overlay in DPL can be up to 9.1%, and well decomposed layout can reduce the variability. For DPL layout decomposition, we propose a multi-objective and flexible framework for stitch minimization, balanced density, and overlay compensation, simultaneously. We use a graph theoretic algorithm for minimum stitch insertion and balanced density. Additional decomposition constraints for overlay compensation are obtained by Integer Linear Programming (ILP). Robust contact decomposition can be obtained with additional constraints. With these constraints, global decomposition is performed using a modified Fiduccia-Mattheyses (FM) graph partitioning algorithm. Experimental results show that the proposed framework is highly scalable and fast: we can decompose all 15 benchmark circuits in five minutes in a density balanced fashion, while an ILP-based approach can finish only the smallest five circuits. In addition, we can remove more than 95% of the timing variation induced by overlay for tested structures. Three-dimensional integration has new manufacturing and design challenges such as device variation due to TSV induced stress and timing corner mismatch between different stacked dies. Since TSV fill material and silicon have different Coefficients of Thermal Expansion (CTE), TSV causes silicon deformation due to different temperatures at chip manufacturing and operating. Therefore, the systematic variation due to TSV induced stress should be considered for robust 3D IC design. We propose systematic TSV stress aware timing analysis and show how to optimize layout for better performance. First, a stress contour map with an analytical radial stress model is generated. Then, the tensile stress is converted to hole and electron mobility variations depending on geometric relations between TSVs and transistors. Mobility variation aware cell library and netlist are generated and incorporated in an industrial timing engine for 3D-IC timing analysis. TSV stress induced timing variations can be as much as 10% for an individual cell. As an application for layout optimization, we can exploit the stress-induced mobility enhancement to improve timing on critical cells. We show that stress-aware perturbation could reduce cell delay by up to 14.0% and critical path delay by 6.5% in our test case. Three-dimensional Clock Tree Synthesis (3D CTS) is one of the main design difficulties in 3D integration because clock network is spreading over all tiers. In 3D CTS, timing corner mismatch between tiers is caused because each tier is manufactured in independent process. Therefore, inter-die variation should be considered to analyze and optimize for paths spreading over several tiers in 3D CTS. In addition, mobility variation of a clock buffer due to stress from TSV can cause unexpected skew which degrades overall chip performance. Therefore, we propose clock period optimization to consider both timing corner mismatch and TSV induced stress. In our experiments, we show that our clock buffer tier assignment reduces clock period variation up to 34.2%, and the most of stress-induced skew can be removed by our stress-aware CTS. Overall, we show that performance gain can be up to 5.7% with the proposed CTS algorithm. As technology scaling continues toward 14nm and 3D-integration, this dissertation addresses several key issues in the design-manufacturing interface, and proposes unified analysis and optimization techniques for effective design and manufacturing integration. / text

The 2008-2010 foreclosure crisis and the Beltline project present two significant forces shaping neighborhoods throughout Atlanta. Both the high foreclosure rates and the promise of public and private investment create conditions for the displacement of existing residents and for the gentrification of the southwest Atlanta neighborhood of Pittsburgh in particular. Through qualitative analysis, including interviews with residents, community leaders, and government officials, the development of overlay analysis maps of Pittsburgh, as well as studying the various stakeholders' perception of risk for gentrification in Pittsburgh, this research examines how and why these stakeholders' perception of the risk of gentrification in Pittsburgh varies, and what these various perceptions mean. Furthermore, it suggests that scholars of the gentrification process should more fully consider the ways in which residents of impacted neighborhoods understand both local and more “global” dynamics of property markets and how various policies seek to mitigate the deleterious effects of gentrification.

The 2008-2010 foreclosure crisis and the Beltline project present two significant forces shaping neighborhoods throughout Atlanta. Both the high foreclosure rates and the promise of public and private investment create conditions for the displacement of existing residents and for the gentrification of the southwest Atlanta neighborhood of Pittsburgh in particular. Through qualitative analysis, including interviews with residents, community leaders, and government officials, the development of overlay analysis maps of Pittsburgh, as well as studying the various stakeholders' perception of risk for gentrification in Pittsburgh, this research examines how and why these stakeholders' perception of the risk of gentrification in Pittsburgh varies, and what these various perceptions mean. Furthermore, it suggests that scholars of the gentrification process should more fully consider the ways in which residents of impacted neighborhoods understand both local and more “global” dynamics of property markets and how various policies seek to mitigate the deleterious effects of gentrification.

A covert communications network (CCN) is a connected, overlay peer-to-peer network used to support communications within a group in which the survival of the group depends on the confidentiality and anonymity of communications, on concealment of participation in the network to both other members of the group and external eavesdroppers, and finally on resilience against disconnection. In this dissertation, we describe the challenges and requirements for such a system. We consider the topologies of resilient covert communications networks that: (1) minimize the impact on the network in the event of a subverted node; and (2) maximize the connectivity of the survivor network with the removal of the subverted node and its closed neighborhood. We analyze the properties of resilient covert networks, propose measurements for determining the suitability of a topology for use in a covert communication network, and determine the properties of an optimal covert network topology. We analyze multiple topologies and identify two constructions that are capable of generating optimal topologies. We then extend these constructions to produce near-optimal topologies that can “grow” as new nodes join the network. We also address protocols for membership management and routing. Finally, we describe the architecture of a prototype system for instantiating a CCN.

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With the increasing demand on multimedia applications over the Internet, and the growing number of mobile smart devices people are using, it is helpful to develop a mobile network architecture that can support multimedia transmission without using infrastructures. We propose that service overlay networks over MANETs can serve as a supplement to the existing 3G/4G networks and Wi-Fi access point networks. In this thesis we present experiment results that show the feasibility of mobile service overlay networks to meet the requirements of multimedia streaming. And also, we improved one of the existing overlay protocols. The improved protocol takes physical location into consideration when establishing connections in the overlay network. It also limits the number of neighbors each node can have, which prevents a particular node from becoming the bottleneck of the network, when connected to too many neighbors. Evaluation results show the new protocol reduces network packet loss rate.