Information and communication systems enter an increasing number of areas of daily lives. Our reliance and dependence on the functioning of such systems is rapidly growing together with the costs and the impact of system failures. At the same time the complexity of hardware and software systems extends to new limits as modern hardware architectures become more and more parallel, dynamic and heterogenous. These trends demand for a closer integration of formal methods and system engineering to show the correctness of complex systems within the design phase of large projects. The goal of this thesis is to introduce a formal holistic approach for modeling, analysis and synthesis of parallel systems that potentially addresses complex system behavior at any layer of the hardware/software stack. Due to the complexity of modern hardware and software systems, we aim to have a hierarchical modeling framework that allows to specify the behavior of a parallel system at various levels of abstraction and that facilitates designing complex systems in an iterative refinement procedure, in which more detailed behavior is added successively to the system description. In this context, the major challenge is to provide modeling formalisms that are expressive enough to address all of the above issues and are at the same time amenable to the application of formal methods for proving that the system behavior conforms to its specification. In particular, we are interested in specification formalisms that allow to apply formal verification techniques such that the underlying model checking problems are still decidable within reasonable time and space bounds. The presented work relies on an exogenous modeling approach that allows a clear separation of coordination and computation and provides an operational semantic model where formal methods such as model checking are well suited and applicable. The channel-based exogenous coordination language Reo is used as modeling formalism as it supports hierarchical modeling in an iterative top-down refinement procedure. It facilitates reusability, exchangeability, and heterogeneity of components and forms the basis to apply formal verification methods. At the same time Reo has a clear formal semantics based on automata, which serve as foundation to apply formal methods such as model checking. In this thesis new modeling languages are presented that allow specifying complex systems in terms of Reo and automata models which yield the basis for a holistic approach on modeling, verification and synthesis of parallel systems. The second main contribution of this thesis are tailored branching-time and alternating time temporal logics as well as corresponding model checking algorithms. The thesis includes results on the theoretical complexity of the underlying model checking problems as well as practical results. For the latter the presented approach has been implemented in the symbolic verification tool set Vereofy. The implementation within Vereofy and evaluation of the branching-time and alternating-time model checker is the third main contribution of this thesis.

Die Informatik ist von besonderer Bedeutung für die Gestaltung unser alltäglichen Lebensumstände und ist eine Schlüsseltechnologie des 21. Jahrhunderts. Die Fakultät für Informatik vertritt dieses Fachgebiet umfassend und kompetent mit anwendungsorientierten Schwerpunktsetzungen. In unseren Forschungsschwerpunkten - Eingebettete selbstorganisierende Systeme - Intelligente multimediale Systeme - Parallele verteilte Systeme bieten wir international wettbewerbsfähige Forschung und Entwicklung zu aktuellen Problemstellungen. Unsere Lehre basiert auf dem Leitmotiv der beständigen Erneuerung aus der Forschung. Hieraus abgeleitet bieten wir zeitgemäße Bachelor- und Masterstudiengänge mit hervorragenden Studienbedingungen. Die Fakultät hat den Anspruch eines möglichst persönlichen Umgangs zwischen Lehrkörper und Studenten. Mit der Schriftenreihe „Chemnitzer Informatik Berichte“ geben wir Einblicke in die Forschungspraxis der Fakultät. Dabei werden unterschiedliche Forschungsthemen aus den drei Forschungsschwerpunkten und allen Professuren der Fakultät vorgestellt. / Computer science, as a key technology of the 21th century, has an exceptional impact on our everyday life and living standards. The Faculty of Computer Science represents this scientific field in a comprehensive and proficient manner with an application-orientated choice of topics. In the fields of - Embedded and self-organizing systems - Intelligent multimedia systems - Parallel and distributed systems we offer research and development for current problems and challenges on an internationally competitive level. The guiding principle of our education is the continuous innovation through advances in research. Consequently, we are able to provide modern Bachelor and Master programs with excellent academic conditions. The faculty strives to provide a maximally personal interaction between students and staff. With the series of publications „Chemnitz Computer Science Reports“ we give insigths into the reasearch practice of the faculty. We present different subjects of research from the tree research fields and all of the professorships of the Faculty of Computer Science.

Eine Herausforderung der Parallelverarbeitung ist das Erreichen von Skalierbarkeit großer paralleler Anwendungen für verschiedene parallele Systeme. Das zentrale Problem ist, dass die Ausführung einer Anwendung auf einem parallelen System sehr gut sein kann, die Portierung auf ein anderes System in der Regel jedoch zu schlechten Ergebnissen führt. Durch die Verwendung des Programmiermodells der parallelen Tasks mit Abhängigkeiten kann die Skalierbarkeit für viele parallele Algorithmen deutlich verbessert werden. Die Programmierung mit parallelen Tasks führt zu Task-Graphen mit Abhängigkeiten zur Darstellung einer parallelen Anwendung, die auch als gemischt-parallele Anwendung bezeichnet wird. Die Grundlage für eine effiziente Abarbeitung einer gemischt-parallelen Anwendung bildet ein geeigneter Schedule, der eine effiziente Abbildung der parallelen Tasks auf die Prozessoren des parallelen Systems vorgibt. Für die Berechnung eines Schedules werden Schedulingalgorithmen eingesetzt. Ein zentrales Problem bei der Bestimmung eines Schedules für gemischt-parallele Anwendungen besteht darin, dass das Scheduling bereits für Single-Prozessor-Tasks mit Abhängigkeiten und ein paralleles System mit zwei Prozessoren NP-hart ist. Daher existieren lediglich Approximationsalgorithmen und Heuristiken um einen Schedule zu berechnen. Eine Möglichkeit zur Berechnung eines Schedules sind layerbasierte Schedulingalgorithmen. Diese Schedulingalgorithmen bilden zuerst Layer unabhängiger paralleler Tasks und berechnen den Schedule für jeden Layer separat. Eine Schwachstelle dieser Schedulingalgorithmen ist das Zusammenfügen der einzelnen Schedules zum globalen Schedule. Der vorgestellte Algorithmus Move-blocks bietet eine elegante Möglichkeit das Zusammenfügen zu verbessern. Dies geschieht durch eine Verschmelzung der Schedules aufeinander folgender Layer. Obwohl eine Vielzahl an Schedulingalgorithmen für gemischt-parallele Anwendungen existiert, gibt es bislang keine umfassende Unterstützung des Schedulings durch Programmierwerkzeuge. Im Besonderen gibt es keine Schedulingumgebung, die eine Vielzahl an Schedulingalgorithmen in sich vereint. Die Vorstellung der flexiblen, komponentenbasierten und erweiterbaren Schedulingumgebung SEParAT ist der zweite Fokus dieser Dissertation. SEParAT unterstützt verschiedene Nutzungsszenarien, die weit über das reine Scheduling hinausgehen, z.B. den Vergleich von Schedulingalgorithmen und die Erweiterung und Realisierung neuer Schedulingalgorithmen. Neben der Vorstellung der Nutzungsszenarien werden sowohl die interne Verarbeitung eines Schedulingdurchgangs als auch die komponentenbasierte Softwarearchitektur detailliert vorgestellt.

We describe an implementation of a multi-threaded NFFT (nonequispaced fast Fourier transform) software library and present the used parallelization approaches. Besides the NFFT kernel, the NFFT on the two-sphere and the fast summation based on NFFT are also parallelized. Thereby, the parallelization is based on OpenMP and the multi-threaded FFTW library. Furthermore, benchmarks for various cases are performed. The results show that an efficiency higher than 0.50 and up to 0.79 can still be achieved at 12 threads.

Die Informatik ist von besonderer Bedeutung für die Gestaltung unser alltäglichen Lebensumstände und ist eine Schlüsseltechnologie des 21. Jahrhunderts. Die Fakultät für Informatik vertritt dieses Fachgebiet umfassend und kompetent mit anwendungsorientierten Schwerpunktsetzungen. In unseren Forschungsschwerpunkten - Eingebettete selbstorganisierende Systeme - Intelligente multimediale Systeme - Parallele verteilte Systeme bieten wir international wettbewerbsfähige Forschung und Entwicklung zu aktuellen Problemstellungen. Unsere Lehre basiert auf dem Leitmotiv der beständigen Erneuerung aus der Forschung. Hieraus abgeleitet bieten wir zeitgemäße Bachelor- und Masterstudiengänge mit hervorragenden Studienbedingungen. Die Fakultät hat den Anspruch eines möglichst persönlichen Umgangs zwischen Lehrkörper und Studenten. Mit der Schriftenreihe „Chemnitzer Informatik Berichte“ geben wir Einblicke in die Forschungspraxis der Fakultät. Dabei werden unterschiedliche Forschungsthemen aus den drei Forschungsschwerpunkten und allen Professuren der Fakultät vorgestellt. / Computer science, as a key technology of the 21th century, has an exceptional impact on our everyday life and living standards. The Faculty of Computer Science represents this scientific field in a comprehensive and proficient manner with an application-orientated choice of topics. In the fields of - Embedded and self-organizing systems - Intelligent multimedia systems - Parallel and distributed systems we offer research and development for current problems and challenges on an internationally competitive level. The guiding principle of our education is the continuous innovation through advances in research. Consequently, we are able to provide modern Bachelor and Master programs with excellent academic conditions. The faculty strives to provide a maximally personal interaction between students and staff. With the series of publications „Chemnitz Computer Science Reports“ we give insigths into the reasearch practice of the faculty. We present different subjects of research from the tree research fields and all of the professorships of the Faculty of Computer Science.

Information and communication systems enter an increasing number of areas of daily lives. Our reliance and dependence on the functioning of such systems is rapidly growing together with the costs and the impact of system failures. At the same time the complexity of hardware and software systems extends to new limits as modern hardware architectures become more and more parallel, dynamic and heterogenous. These trends demand for a closer integration of formal methods and system engineering to show the correctness of complex systems within the design phase of large projects. The goal of this thesis is to introduce a formal holistic approach for modeling, analysis and synthesis of parallel systems that potentially addresses complex system behavior at any layer of the hardware/software stack. Due to the complexity of modern hardware and software systems, we aim to have a hierarchical modeling framework that allows to specify the behavior of a parallel system at various levels of abstraction and that facilitates designing complex systems in an iterative refinement procedure, in which more detailed behavior is added successively to the system description. In this context, the major challenge is to provide modeling formalisms that are expressive enough to address all of the above issues and are at the same time amenable to the application of formal methods for proving that the system behavior conforms to its specification. In particular, we are interested in specification formalisms that allow to apply formal verification techniques such that the underlying model checking problems are still decidable within reasonable time and space bounds. The presented work relies on an exogenous modeling approach that allows a clear separation of coordination and computation and provides an operational semantic model where formal methods such as model checking are well suited and applicable. The channel-based exogenous coordination language Reo is used as modeling formalism as it supports hierarchical modeling in an iterative top-down refinement procedure. It facilitates reusability, exchangeability, and heterogeneity of components and forms the basis to apply formal verification methods. At the same time Reo has a clear formal semantics based on automata, which serve as foundation to apply formal methods such as model checking. In this thesis new modeling languages are presented that allow specifying complex systems in terms of Reo and automata models which yield the basis for a holistic approach on modeling, verification and synthesis of parallel systems. The second main contribution of this thesis are tailored branching-time and alternating time temporal logics as well as corresponding model checking algorithms. The thesis includes results on the theoretical complexity of the underlying model checking problems as well as practical results. For the latter the presented approach has been implemented in the symbolic verification tool set Vereofy. The implementation within Vereofy and evaluation of the branching-time and alternating-time model checker is the third main contribution of this thesis.

This paper demonstrates an approach for passive alignment and assembly of link components for board-level very-short range optical interconnects. This interchip optical link is based on planar polymeric multimode waveguides and glassbased electro-optical transceivers. The main aim of the work is the investigation of assembly processes of link components in order to fulfill the tolerance requirements using passive alignment. The optical characterization in regard to the optical coupling between link components will define the tolerances for the alignment process. This optical analysis is based on measurements of spatial coupling characteristics. The influence of assembly tolerances on the coupling efficiency is investigated. Flip-chip assembly of electro-optical devices on the glass interposer and of the glass interposer on optical overlay is presented to prove the implementation of the concept.

This paper discusses the technology development for integration of parallel optical interconnects on board-level, including the active and passive optical components as well as the electrical integrated circuitry. The inter-chip link is based on planar polymeric optical multimode waveguides with integrated out-of-plane coupling optics and optical transceiver subassemblies based on glass interposer. Integration of polymeric waveguides on flexible substrates will be shown since the realization of an overlay optical substrate enhances the yield and testability of the final hybrid electrooptical printed circuit board (EOPCB). Realized on-board waveguides feature low insertion loss (minimum attenuation coefficient of below 0.1 dB/cm). For short planar waveguides (Lwaveguide = 9 cm) error free transmission (BER < 10-12) up to 30 Gbit/s was achieved. The development of glass interposer passive optical coupling structures for VCSEL-based short-distance links will be described.

This paper presents the development and mathematical implementation of a production scheduling model utilizing mixed-integer linear programming (MILP). A simplified model of a real-world multi-product batch plant constitutes the basis. The paper shows practical extensions to the model, resulting in a digital twin of the plant. Apart from sequential arrangement, the final model contains maintenance periods, campaign planning and storage constraints to a limited extend. To tackle weak computational performance and missing model features, a condensed mathematical formulation is introduced at first. After stating that these measures do not suffice for applicability in a restrained time period, a novel solution strategy is proposed. The overall non-iterative algorithm comprises a multi-step decomposition approach, which starts with a reduced scope and incrementally complements the schedule in multiple subproblem stages. Each of those optimizations holds less decision variables and makes use of warmstart information obtained from the predecessor model. That way, a first feasible solution accelerates the subsequent improvement process. Furthermore, the optimization focus can be shifted beneficially leveraging the Gurobi solver parameters. Findings suggest that correlation may exist between certain characteristics of the scheduling scope and ideal parameter settings, which yield potential for further investigation. Another promising area for future research addresses the concurrent multi-processing of independent MILPs on a single machine. First observations indicate that significant performance gains can be achieved in some cases, though sound dependencies were not discovered yet.

Tile-based many-core architectures are extensively used in modern system-on-chip designs to achieve scalable computing performance with adequate energy efficiency. Heterogeneity is the key element to boost computing performance and keep energy consumption under certain limits for several application domains. However, the steady increase of using many custom heterogeneous tiles leads to an expansion in design and integration cost with limited tiles re-usability. The recent widespread of open-source RISC-V ISA provides the potential to develop modular compute units that can be used for many application domains with high reduction in non-recurring engineering costs. The motivation of this work is to bring design modularity and adaptability features for heterogeneous tile-based many-core architectures by increasing their flexibility to realize different many-core configurations with less design time and costs. In this work, AGILER is proposed as an adaptive tile-base many-core architecture for heterogeneous RISC-V based processors. The proposed architecture consists of modular and adaptable heterogeneous multi-/single-core compute tiles that supports 32-/64-bit RISC-V ISAs with different memory hierarchies. Inter-tile communication is developed based on a scalable network-on-chip architecture to achieve a high degree of system scalability. AGILER supports run-time adaptation through a custom internal reconfiguration manager for dynamic and partial reconfiguration over Xilinx FPGAs. Evaluation results demonstrate that the proposed architecture features a scalable computing performance up to 685 MOPS for 8 x 32-bit tiles and 316 MOPS for 8 x 64-bit tiles with a scalable memory bandwidth up to 7.4 GB/s. AGILER is evaluated on Xilinx Virtex UltrascaleC FPGA with a maximum reconfiguration time of 38.1 ms for a single compute tile.