The benefits of good loop tuning in the process industries have long been recognized. Ensuring that controllers are kept well-configured despite changes in process dynamics can bring energy and material savings, improved product quality as well as reduced downtime. A number of loop tuning packages therefore exist that can, on demand, check the state of a loop and adjust the controller as necessary. These methods generally apply some form of upset to the process to identify the current plant dynamics, against which the controller can then be evaluated. A simple approach to the automatic tuning of PI controllers injects variable frequency sinewaves into the loop under normal plant operation. The method employs a phase-locked loop-based device called a phase-frequency/estimation and uses 'design-point' rules, where the aim is for the Nyquist locus of the loop to pass through a particular point on the complex plane. A number of advantages are offered by the scheme: it can carry out both 'one shot' tuning and continuous adaptation, the latter even with the test signal set to a lower amplitude than that of noise. A published article is included here that extends the approach to PID controllers, with simulations studies and real-life test showing the method to work consistently well for a for a wide range of typical process dynamics, the closed-loop having a response that compares well with that produced by standard tuning rules. The associated signal processing tools are tested by applying them to the transmitter of a Coriolis mass-flow meter. Schemes are devised for the tracking and control of the second mode of measurementtube oscillation alongside the so-called 'driven mode', at which the tubes are usually vibrated, leading to useful information being made available for measurement correction purposes. Once a loop has been tuned, it is important to assess it periodically and to detect any performance losses resulting from events such as changes in process or disturbance dynamics and equipment malfunction such as faulty sensors and actuators. Motivated by the effective behaviour of the controller tuners, a loop monitor developed here, also using probing sinewaves coupled with 'design-point' ideas. In this application, the effect on the process must be minimal, so the device must work with lower still SNRs. Thus it is practical to use a fixed-frequency probing signal, together with a different tool set for tracking it. An extensive mathematical framework is developed describing the statistical properties of the signal parameter estimates, and those of the indices derived from these estimates indicating the state of the loop. The result is specific practical guidelines for the application of the monitor (e.g. for the choices of test signal amplitude and test duration). Loop monitoring itself has traditionally been carried out by passive methods that calculate various performance indicators from routine operating data. Playing a central role amongst these metrics is the Harris Index (HI) and its variants, which compare the output variance to a 'minimum achievable' figure. A key advantage of the active monitor proposed here is that it is able not only to detect suboptimal control but also to suggest how the controller should be adjusted. Moreover, the monitor’s index provides a strong indication of changes in damping factor. Through simple adjustments to the algorithm (by raising the amplitude of the test signal or adding high frequency dither to the control signal), the method can be applied even in the presence of actuator non-linearity, allowing it to identify the cause of performance losses. This is confirmed by real-life trials on a non-linear flow rig.

This thesis presents the CMOS integer-N frequency synthesizer for 5 GHz WCDMA applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection, and a pulse-swallow divider. In pulse-swallow divider, this thesis use true single phase clock DFF proposed by Yuan and Svensson to work on high frequency region and to save the circuit area and power. This thesis also proposes an auto-band selection circuit to control the output frequency more precise and easier, and it can also reduce the frequency drift effect caused by technology process or temperature variation.

This thesis presents a low power consumption, low phase noise, and fast locking CMOS fractional-N frequency synthesizer with optimalied voltage-controlled oscillator. The frequency synthesizer is designed in a TSMC 0.18£gm CMOS 1P6M technology process. It can be used for IEEE 802.16e mobile Wimax¡¦s devices and outputing frequency is ranged from 2.3GHz to 2.45GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump (CP), a low-pass loop filter (LPF), a voltage-controlled oscillator (VCO), a multi-modulus divider, and a delta-sigma modulator (DSM). In system design, two voltage-controlled oscillators we presented to achieve low power consumption, low phase noise, and stable output swing. Delta-sigma modulator (DSM) is adopted to produce high frequency resolution, switching over frequency fast and very low phase noise. This thesis proposes a switch circuit which can reduce the lock of time of synthesizer. In the mean time it also reduces the emergence of lose lock.

Phase Synthesis is a fundamental operation in Smart Antennas and other Phased Array systems based on beamforming. There are increasing commercial applications for Integrated Phased Arrays due to their low cost, size and power and also because the RF and digital signal processing can be performed on the same chip. These low cost beamforming applications have augmented interest in Coupled Phase Locked Loop (CPLL) systems for Phase Synthesis. Previous work on the implementation of Phase Synthesis systems using Coupled PLLs for low cost beamforming had the constraint of a limited phase range of ±90°. The idea behind the thesis is that this phase synthesis range can be increased to ±180° through the use of PLLs employing Phase Frequency Detectors(PFDs), which is a significant improvement over conventional coupled-PLL systems. This work presents the detailed design and measurement results for a phase synthesizer using Coupled PLLs for achieving phase shift in the range of ±180°. Several Coupled PLL architectures are investigated and their advantages and limitations are evaluated in terms of frequency controllability, phase difference synthesis control and phase noise of the systems. A two-PLL system implementation using off the shelf components is presented, which generates a steady-state phase difference in the range ±180° using an adjustable DC control current. This is the proof of concept for doing an IC design for a Coupled Phase Locked Loop system. Commercial applications in the Wireless Medical Telemetry Service (WMTS) band motivate the design of a CPLL system in the 608-614 MHz band. The design methodology is presented which shows the flowchart of the IC design process from the system design specifications to the transistor level design. MATLAB simulations are presented to model the system performance quickly. VerilogA modeling of the CPLL system is performed followed by the IC design of the system and each block is simulated under different process and temperature corners. The transistor level design is then evaluated for its performance in terms of phase difference synthesis and phase noise and compared with the initial MATLAB analysis and improved iteratively. The CPLL system is implemented in IBM 130nm CMOS process and consumes 40mW of power from a 1.2V supply with a phase noise performance of -88 dBc/Hz for 177° phase generation.

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Power limits on future high-performance computing (HPC) systems will constrain applications. However, HPC applications do not consume constant power over their lifetimes. Thus, applications assigned a fixed power bound may be forced to slow down during high-power computation phases, but may not consume their full power allocation during low-power I/O phases. This paper explores algorithms that leverage application semantics-phase frequency, duration and power needs-to shift unused power from applications in I/O phases to applications in computation phases, thus improving system-wide performance. We design novel techniques that include explicit staggering of applications to improve power shifting. Compared to executing without power shifting, our algorithms can improve average performance by up to 8% or improve performance of a single, high-priority application by up to 32%.

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A digital system is often required to operate under a specific frequency. A ring oscillator can be helpful in this circumstance because it can generate a signal with a specific frequency. However, a ring oscillator is also sensitive to the environment temperature. With the increasing requirement of accuracy and stability, many approaches appear worldwide to make a temperature-insensitive ring oscillator. This thesis project presents an approach to compensate the temperature effect on a Current Starved Ring Oscillator(CSRO). More concretely, we researched how to achieve temperature compensation for CSRO in a digitally-controlled configuration. A Phase Frequency Detector (PFD) block is adapted to sense the frequency difference between the reference frequency and CSRO frequency. Two Charge Pumps (CP)are used to quantify the difference in voltage signal. A Dynamic Comparator block compares the signals from CPs. A following Bidirectional Counter block can count up or down to change the current in CSRO by a four-bit signal. In the end, the CSRO can generate an oscillating signal at the appropriate frequency after some adaptation time. This proposed circuit was realized with AMS 0.35 um CMOS technology and simulated using the Cadence tools. Power consumption, temperature compensation analysis and voltage supply compensation analysis under different temperatures are also performed in the project.