No description available.

A Physical Unclonable Function (PUF) has shown a lot of promise to solve many security issues due to its ability to generate a random yet chip-unique secret in the form of an identifier or a key while resisting cloning attempts as well as physical tampering. It is a hardware-based challenge-response function which maps its responses to its challenges exploiting complex statistical variation in the logic and interconnect inside integrated circuits (ICs). An efficient PUF should generate a key that varies randomly from one chip to another. At the same time, it should reliably reproduce a key from a chip every time the key is requested from that chip. Moreover, a PUF should be robust to thwart any attack that aims to reveal its key. Designing an efficient PUF having all these qualities with a low cost is challenging. Furthermore, the efficiency of a PUF needs to be validated by characterizing it over a group of chips. This is because a PUF circuit is supposed to be instantiated in several chips, and whether it can produce a chip-unique identifier/key or not cannot be validated using a single chip. The main goal of this research is to propose a systematic approach to build a random, reliable, and robust PUF incurring minimal cost. With this objective, we first formulate a novel PUF system model that uncouples PUF measurement from PUF identifier formation. The proposed model divides PUF operation into three separate but related components. We show that the three PUF quality factors, randomness, reliability, and robustness, can be improved at each component of the system model resulting in an overall improvement of a PUF. We proposed three PUF enhancement techniques using the system model in this research. The proposed techniques showed significant improvements in a PUF. Second, we present a large-scale PUF characterization method to validate the efficiency of a PUF as a secure primitive. A compact and portable method measured a sizable set of around 200 chips. We also performed experiments to test a PUF against variations in operating conditions (temperature, supply voltage) and circuit aging. Third, we propose a method that can evaluate and compare the performance of different PUFs irrespective of their underlying working principles. This method can help a designer to select a PUF that is the most suitable one for a particular application. Finally, a novel PUF that exploits the variability in the pipeline of a microprocessor is presented. This PUF has a very low area cost while it can be easily integrated using software programs in an application having a microprocessor. / Ph. D.

京都大学 / 新制・課程博士 / 博士(情報学) / 甲第24746号 / 情博第834号 / 新制||情||140(附属図書館) / 京都大学大学院情報学研究科通信情報システム専攻 / (主査)教授 佐藤 高史, 教授 橋本 昌宜, 教授 新津 葵一 / 学位規則第4条第1項該当 / Doctor of Informatics / Kyoto University / DFAM

No description available.

Field Programmable Gate Arrays (FPGAs) are reconfigurable, high-performing devices that are often used in critical applications. However, like all semiconductors, FPGAs experience transistor aging that can lower performance and lead to device failures. Additionally, device aging also has several security implications. Therefore, understanding the aging mechanisms behind transistor aging is necessary to ensure the reliability of FPGAs. However, current aging studies either rely on simulation alone or are unable to isolate aging effects on specific elements within the FPGA. This dissertation uses the reconfigurability of FPGAs to develop novel aging techniques that allow for the targeted aging of specific areas of the FPGA fabric. This allows us to manipulate the performance variation of a device, which allows for several interesting security applications. In addition, we use precise characterization methods that, when combined with our fine-grained aging techniques, allow us to isolate the effects of aging on individual paths and elements within the FPGA. This provides valuable insights into FPGA aging which can be used to develop new aging mitigation strategies. This dissertation is comprised of five major contributions. The first contribution uses thousands of short circuits to induce a non-uniform slowdown of an FPGA's programmable fabric. The second contribution demonstrates how modifier circuits can be inserted into a region of short circuits to perform more precise aging to a targeted region and allow us to manipulate performance variation at the tile level of an FPGA. The third contribution uses our targeted aging technique to demonstrate two security applications: frequency watermark and cloning a ring oscillator physical unclonable function (RO PUF) on an FPGA. The fourth contribution uses carefully crafted stress circuits and precise characterization methods to isolate the effects of transistor aging on individual paths within the FPGA. The final contribution uses elements of our precise characterization techniques to create a more reliable configurable RO PUF (CRO PUF) for cryptographic key generation on FPGAs.

Advancement in cryptography over the past few decades has enabled a spectrum of security mechanisms and protocols for many applications. Despite the algorithmic security of classic cryptography, there are limitations in application and implementation of standard security methods in ultra-low energy and resource constrained systems. In addition, implementations of standard cryptographic methods can be prone to physical attacks that involve hardware level invasive or non-invasive attacks. Physical unclonable functions (PUFs) provide a complimentary security paradigm for a number of application spaces where classic cryptography has shown to be inefficient or inadequate for the above reasons. PUFs rely on intrinsic device-dependent physical variation at the microscopic scale. Physical variation results from imperfection and random fluctuations during the manufacturing process which impact each device’s characteristics in a unique way. PUFs at the circuit level amplify and capture variation in electrical characteristics to derive and establish a unique device-dependent challenge-response mapping. Prior to this work, PUF implementations were unsuitable for low power applications and vulnerable to wide range of security attacks. This doctoral thesis presents a coherent framework to derive formal requirements to design architectures and protocols for PUFs. To the best of our knowledge, this is the first comprehensive work that introduces and integrates these pieces together. The contributions include an introduction of structural requirements and metrics to classify and evaluate PUFs, design of novel architectures to fulfill these requirements, implementation and evaluation of the proposed architectures, and integration into real-world security protocols. First, I formally define and derive a new set of fundamental requirements and properties for PUFs. This work is the first attempt to provide structural requirements and guideline for design of PUF architectures. Moreover, a suite of statistical properties of PUF responses and metrics are introduced to evaluate PUFs. Second, using the proposed requirements, new and efficient PUF architectures are designed and implemented on both analog and digital platforms. In this work, the most power efficient and smallest PUF known to date is designed and implemented on ASICs that exploits analog variation in sub-threshold leakage currents of MOS devices. On the digital platform, the first successful implementation of Arbiter-PUF on FPGA was accomplished in this work after years of unsuccessful attempts by the research community. I introduced a programmable delay tuning mechanism with pico-second resolution which serves as a key component in implementation of the Arbiter-PUF on FPGA. Full performance analysis and comparison is carried out through comprehensive device simulations as well as measurements performed on a population of FPGA devices. Finally, I present the design of low-overhead and secure protocols using PUFs for integration in lightweight identification and authentication applications. The new protocols are designed with elegant simplicity to avoid the use of heavy hash operations or any error correction. The first protocol uses a time bound on the authentication process while second uses a pattern-matching index-based method to thwart reverseengineering and machine learning attacks. Using machine learning methods during the commissioning phase, a compact representation of PUF is derived and stored in a database for authentication.

abstract: Programmable metallization cell (PMC) technology employs the mechanisms of metal ion transport in solid electrolytes (SE) and electrochemical redox reactions in order to form metallic electrodeposits. When a positive bias is applied to an anode opposite to a cathode, atoms at the anode are oxidized to ions and dissolve into the SE. Under the influence of the electric field, the ions move to the cathode and become reduced to form the electrodeposits. These electrodeposits are filamentary in nature and persistent, and since they are metallic can alter the physical characteristics of the material on which they are formed. PMCs can be used as next generation memories, radio frequency (RF) switches and physical unclonable functions (PUFs). The morphology of the filaments is impacted by the biasing conditions. Under a relatively high applied electric field, they form as dendritic elements with a low fractal dimension (FD), whereas a low electric field leads to high FD features. Ion depletion effects in the SE due to low ion diffusivity/mobility also influences the morphology by limiting the ion supply into the growing electrodeposit. Ion transport in SE is due to hopping transitions driven by drift and diffusion force. A physical model of ion hopping with Brownian motion has been proposed, in which the ion transitions are random when time window is larger than characteristic time. The random growth process of filaments in PMC adds entropy to the electrodeposition, which leads to random features in the dendritic patterns. Such patterns has extremely high information capacity due to the fractal nature of the electrodeposits. In this project, lateral-growth PMCs were fabricated, whose LRS resistance is less than 10Ω, which can be used as RF switches. Also, an array of radial-growth PMCs was fabricated, on which multiple dendrites, all with different shapes, could be grown simultaneously. Those patterns can be used as secure keys in PUFs and authentication can be performed by optical scanning. A kinetic Monte Carlo (KMC) model is developed to simulate the ion transportation in SE under electric field. The simulation results matched experimental data well that validated the ion hopping model. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015

abstract: Counterfeiting of goods is a widespread epidemic that is affecting the world economy. The conventional labeling techniques are proving inadequate to thwart determined counterfeiters equipped with sophisticated technologies. There is a growing need of a secure labeling that is easy to manufacture and analyze but extremely difficult to copy. Programmable metallization cell technology operates on a principle of controllable reduction of a metal ions to an electrodeposit in a solid electrolyte by application of bias. The nature of metallic electrodeposit is unique for each instance of growth, moreover it has a treelike, bifurcating fractal structure with high information capacity. These qualities of the electrodeposit can be exploited to use it as a physical unclonable function. The secure labels made from the electrodeposits grown in radial structure can provide enhanced authentication and protection from counterfeiting and tampering. So far only microscale radial structures and electrodeposits have been fabricated which limits their use to labeling only high value items due to high cost associated with their fabrication and analysis. Therefore, there is a need for a simple recipe for fabrication of macroscale structure that does not need sophisticated lithography tools and cleanroom environment. Moreover, the growth kinetics and material characteristics of such macroscale electrodeposits need to be investigated. In this thesis, a recipe for fabrication of centimeter scale radial structure for growing Ag electrodeposits using simple fabrication techniques was proposed. Fractal analysis of an electrodeposit suggested information capacity of 1.27 x 1019. The kinetics of growth were investigated by electrical characterization of the full cell and only solid electrolyte at different temperatures. It was found that mass transport of ions is the rate limiting process in the growth. Materials and optical characterization techniques revealed that the subtle relief like structure and consequently distinct optical response of the electrodeposit provides an added layer of security. Thus, the enormous information capacity, ease of fabrication and simplicity of analysis make macroscale fractal electrodeposits grown in radial programmable metallization cells excellent candidates for application as physical unclonable functions. / Dissertation/Thesis / Masters Thesis Materials Science and Engineering 2017

The proliferation of embedded systems into nearly every aspect of modern infrastructure and society has seen their deployment in such diverse roles as monitoring the power grid and processing commercial payments. Software intellectual property (SWIP) is a critical component of these increasingly complex systems and represents a significant investment to its developers. However, deeply immersed in their environment, embedded systems are difficult to secure. As a result, developers want to ensure that their SWIP is protected from being reverse engineered or stolen by unauthorized parties. Many techniques have been proposed to address the issue of SWIP protection for embedded systems. These range from secure memory components to complete shifts in processor architectures. While powerful, these approaches often require the development of systems from the ground up or the application of specialized and often expensive hardware components. As a result they are poorly suited to address the security concerns of legacy embedded systems or systems based on commodity components. This work explores the protection of SWIP on heavily constrained, legacy and commodity embedded systems. We accomplish this by evaluating a generic embedded system to identify the security concerns in the context of SWIP protection. The evaluation is applied to determine the limitations of a software only approach on a real world legacy embedded system that lacks any specialized security hardware features. We improve upon this system by developing a prototype system using only commodity components. Finally we propose a Portable Embedded Software Intellectual Property Security (PESIPS) system that can easily be deployed as a framework on both legacy and commodity systems. / Master of Science

Orientadores: Guido Costa Souza de Araújo, Mario Lúcio Côrtes / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-21T20:47:12Z (GMT). No. of bitstreams: 1 Santana_MarceloFontes_M.pdf: 4262688 bytes, checksum: 3e2635e36cd3272eb4bd09c07b05bf63 (MD5) Previous issue date: 2012 / Resumo: O resumo, poderá ser visualizado no texto completo da tese digital / Abstract The abstract is available with the full electronic document / Mestrado / Ciência da Computação / Mestre em Ciência da Computação