Submitted by Pedro Barros (pedro.silvabarros@ufpe.br) on 2018-08-30T20:00:39Z No. of bitstreams: 2 license_rdf: 811 bytes, checksum: e39d27027a6cc9cb039ad269a5db8e34 (MD5) DISSERTAÇÃO Rowan Henrique Sarmento Silveira.pdf: 3135239 bytes, checksum: f9995bb40cf70914b32cab37280bc4e7 (MD5) / Approved for entry into archive by Alice Araujo (alice.caraujo@ufpe.br) on 2018-09-17T20:12:23Z (GMT) No. of bitstreams: 2 license_rdf: 811 bytes, checksum: e39d27027a6cc9cb039ad269a5db8e34 (MD5) DISSERTAÇÃO Rowan Henrique Sarmento Silveira.pdf: 3135239 bytes, checksum: f9995bb40cf70914b32cab37280bc4e7 (MD5) / Made available in DSpace on 2018-09-17T20:12:23Z (GMT). No. of bitstreams: 2 license_rdf: 811 bytes, checksum: e39d27027a6cc9cb039ad269a5db8e34 (MD5) DISSERTAÇÃO Rowan Henrique Sarmento Silveira.pdf: 3135239 bytes, checksum: f9995bb40cf70914b32cab37280bc4e7 (MD5) Previous issue date: 2017-06-27 / CNPq / O Pixel Art é um estilo de representação visual nostálgico e simplificado, que remete aos primeiros jogos de videogame e que ainda hoje possui expressividade no mercado de jogos digitais, principalmente através do cenário indie. Caracterizado por baixas resoluções gráficas, seus jogos podem encontrar limitações em representar de forma plena a aparência de personagens, não fazendo uso de todo o seu potencial empático, que por sua vez, ajuda a expressar a personalidade da personagem e direcionar o olhar do jogador em relação à mesma, agindo como um importante elemento imersivo. Este trabalho visa, através de exploração bibliográfica e de casos representativos, resultar em um referencial de design que facilite a configuração de personagens nesse contexto. Para tanto, divide-se em três etapas: Na etapa introdutória (que envolve os três primeiros capítulos), são lançados os conceitos-base para a investigação proposta, partindo principalmente da definição do pixel art e a ação da empatia na relação entre personagem e jogador; a etapa investigativa envolve os três capítulos seguintes e revela-se como a mais determinante deste trabalho, onde são investigados elementos diversos para a construção empática da personagem pixel art, como (respectivamente) elementos expressivos do corpo humano, representação gráfica de personagens e artifícios configurativos passíveis de serem utilizados para alavancar seu potencial empático dentro do jogo. A terceira etapa engloba o último capítulo e a conclusão deste trabalho: trata-se da verificação de uso dos principais elementos investigados nos capítulos anteriores, partindo de um checklist de enunciados relevantes nos vinte jogos pixel art voltados a personagens mais baixados na plataforma on-line Steam (Março de 2017), no intuito de perceber a extensão de suas aplicações. Tal verificação traz um retorno positivo, de forma que foi possível observar a utilização de grande parcela dos elementos e artifícios explorados na configuração dos jogos analisados. / The Pixel Art is a simplified and nostalgic visual representation style dating back to the beginning of the gaming industry, with considerably expressiveness to the present day. Known for its low graphic resolutions, pixel art games may find some constraints in fully representing a character’s appearance,resulting in its low use of empathic potential. The emphatic potential improves the expressiveness of a character traits, therefore it directs the player’s gaze through their looks and behavior as a important immersion feature. This work aims to result in a design reference to facilitate configurative processes through a bibliographic and representative cases exploration. For that, it is split in three main steps: for the introductory one (involving the three first chapters), the necessary base-concepts are exploited for the proposed investigation, encompassing subjects such as pixel art definitions and the empathic relation between player and character; the second step is a investigative one: it embraces the three next chapters and reveals itself as the most important for this work, since it holds elements such as human expressive features, character graphic representation and representational tips for boosting character design by empathic perspective (respectively), resulting in configurative tactics for a design reference. The third step relates to both last chapter and conclusion of this work: it’s about a use verification of the main elements found throughout the research done on the previous chapters, by a checklist of relevant statements applied to twenty most-downloaded character-based pixel art indie games found on Steam on-line platform (on March, 2017). Such verification is taken in order to perceive the usage extension of the configurative tactics previously found, turning out as a positive feedback, since it was possible to verify the presence of a expressive amount of those tactics in the analyzed games.

Aujourd’hui, les capteurs d’image CMOS sont quasi exclusivement architecturés autour de pixels analogiques. Une transition vers des pixels purement numériques permettrait d’améliorer significativement les performances des imageurs. Malheureusement, une telle approche est difficilement envisageable car elle entraine un pixel surdimensionné et inutilisable pour le marché grand public. Une des voies prometteuses pour résoudre ce problème d’intégration des pixels est de réfléchir non plus en deux dimensions (2D), mais en trois dimensions (3D), en répartissant les différentes fonctionnalités sur plusieurs wafers interconnectés.Ainsi, les travaux présentés dans ce manuscrit décrivent la conception d’un capteur d’image purement numérique en technologie CMOS 3D-IC 130 nm Tezzaron. Ce capteur est architecturé autour d’un pixel numérique intégrant une modulation sigma delta du premier ordre sur 10 bits de résolution maximale. L’étude exhaustive des différents blocs constituant le pixel nous a permis de proposer au final une solution garantissant une surface maitrisée de silicium : taille finale de pixel de 32,5 μm × 32,5 μm pour un facteur de remplissage de plus de 80 %. Au niveau des performances brutes, la simulation du pixel a révélé de bons résultats : consommation de 11 μA/pixel, rapport signal sur bruit de 60 dB, nombre effectif de bits d'environ 7,2 bits, non linéarité différentielle maximale et minimale de +1,37 /-0,73 (pour 10 bits) et une non linéarité intégrale maximale et minimale de +2,447/-3,5 (pour 10 bits). / Nowadays, CMOS image sensors are almost exclusively architectured around analog pixels. A transition to purely digital pixels would significantly improve the performances of imagers. Unfortunately, such an approach is difficult to consider because it causes an oversized and unusable pixel for the consumer market. One of the promising ways to solve this problem of pixel integration is to think not only in 2D dimensions, but in 3D dimensions by distributing the different functionalities on several interconnected wafers.Thus, the work presented in this manuscript describes the design of a purely digital image sensor in CMOS 3D-IC 130 nm Tezzaron technology. This sensor is architectured around a digital pixel integrating a first order sigma delta modulation on 10 bits of maximum resolution. The exhaustive study of the different blocks constituting the pixel allowed us to finally propose a solution guaranteeing a contained surface of silicon: final pixel size of 32.5 μm × 32.5 μm with a fill factor of at least 80 %. Regarding performances, the pixel simulations showed good results: 11 μA/pixel consumption, 60 dB signal-to-noise ratio, 7.2 effective number of bits, maximum and minimum differential nonlinearity of +1,37/-0,73 (for 10 bits) and a maximum and minimum integral nonlinearity of + 2,447/-3,5 (for 10 bits).

Ce travail contribue au programme de recherche et de développement d'un capteur CMOS à pixel qui pourrait satisfaire pleinement les spécifications du nouvel ITS (Inner Tracking System : trajectomètre interne) de l'expérience ALICE. Afin de briser les limites de la CPS de pointe, une technologie CMOS 0.18 µm à quatre puits a été explorée. Les capteurs fabriqués dans cette nouvelle technologie ont montré une meilleure tolérance aux radiations que les capteurs réalisés dans une technologie CMOS 0.35 µm plus ancienne. En outre, cette nouvelle technologie offre la possibilité d’implémenter des transistors de type P dans chaque pixel sans dégrader la capacité de collection de la diode. Il devient donc possible d’intégrer un discriminateur dans chaque pixel et obtenir un pixel à sortie binaire. En conséquence, la consommation sera largement réduite. De plus, le temps de traitement de la ligne peut être potentiellement réduit. Un premier prototype de petite taille, intitulé AROM-0, a été conçu et fabriqué afin d’étudier la faisabilité de la discrimination de signal dans un petit pixel. Dans ce prototype, chaque pixel de surface 22 × 33 µm2 contient une diode de détection, un préamplificateur et un discriminateur à tension d’offset compensée. La performance de bruit des différentes versions de pixels dans le capteur AROM-0 a été évaluée. Ensuite sera détaillé le développement des capteurs AROM-1. Ce sont les capteurs intermédiaires vers le capteur final proposé par notre groupe. Ils ont deux objectifs principaux, l’un est de valider les optimisations de conception du pixel et l’autre est de mettre en place une architecture du capteur évolutive intégrant l’intelligence nécessaire dans le circuit. Cette thèse présente en détail la conception et les résultats de mesure de ces capteurs AROM. / This work is part of the R&D program aimed for a CMOS pixel sensor (CPS) complying with the requirements of the upgrade of the inner tracking system (ITS) of the ALICE experiment. In order break the limitations of the state-of-the-art CPS, a 0.18 µm quadruple-well CMOS process was explored. Besides an enhanced radiation tolerance, with respect to the former sensors fabricated in a 0.35 µm process, the sensor based on this new process allows for full CMOS capability inside the pixel without degradation of the detection efficiency. Therefore, the signal discrimination, which was formerly performed at the column level, can be integrated inside the pixel. As a result, the readout speed and power consumption can be greatly improved as compared to the CPS with column-level discrimination. This work addresses the feasibility study of achieving the signal discrimination withina small pixel (i.e. 22 × 33 µm2), via the prototype named AROM-0. The pixel of AROM-0 contains a sensing diode, a pre-amplifier and an offset compensated discriminator. The noise performance of the various pixel versions implemented in AROM-0 was evaluated. The study was further pursued with the AROM-1 prototypes, incorporating the optimized pixel designs and the necessary on-chip intelligence to approach the final sensor we have proposed for the ALICE-ITS upgrade. This thesis presents in detail the design and the measurement results of these AROM sensors.

Abstract Research on X-ray imaging sensors and systems have been carried out for several decades. To make these X-ray scanners smaller with better performance and higher operating speed is an important subject for scientific research and industrial applications. This thesis covers a whole X-ray line-scan camera system. Special attention is given to the smart sensor micromodule design and processing technology. The smart sensor micromodule is an integrated sensor card that includes both silicon X-ray sensor array and signal-processing integrated circuits, which can perform the functions of both an optical sensor and an analog signal processor. Digital signal processing (DSP) made by application specific integrated circuits (ASICs) is also covered in this thesis. Processing technology of the photodiode array, design of the integrated circuit, design and packaging of the micromodules are presented in this thesis. The mechanism of photodiode leakage current is studied in detail. Measured results show that the leakage current level of the photodiode array achieves 80 pA/cm2 under zero bias condition, which outperforms the best photodiode reported so far. The algorithm of the digital signal processing is also studied. The X-ray scanning system can achieve 2 m/s scanning speed with a spatial resolution of 400 mm.

The motivation of the research presented in this thesis is to investigate image processing algorithms utilising various SIMD parallel devices, especially massively parallel Cellular Processor Arrays (CPAs), to accelerate their processing speed. Various SIMD processors with different architectures are reviewed, and their features are analysed. The different types of parallelisms contained in image processing tasks are also analysed, and the methodologies to exploit date-level parallelisms are discussed. The efficiency of the pixel-per-processor architecture used in computer vision scenarios are discussed, as well as its limitations. Aiming to solve the problem that CPA array dimensions are usually smaller than the resolution of the images needed to be processed, a “coarse grain mapping method” is proposed. It provides the CPAs with the ability of processing images with higher resolution than the arrays themselves by allowing CPAs to process multiple pixels per processing element. It is completely software based, easy to implement, and easy to program. To demonstrate the efficiency of pixel-level parallel approach, two image processing algorithms specially designed for pixel-per-processor arrays are proposed: a parallel skeletonization algorithm based on two-layer trigger-wave propagation, and a parallel background detection algorithm. Implementations of the proposed algorithms using different platforms (i.e. CPU, GPU and CPA) are proposed and evaluated. Evaluation results indicate that the proposed algorithms have advantages both in term of processing speed and result quality. This thesis concludes that pixel-per-processor architecture can be used in image processing (or computer vision) algorithms which emphasize analysing pixel-level information, to significantly boost the processing speed of these algorithms.

3D silicon pixel detectors are a novel technology where the electrodes penetrate the sili- con bulk perpendicularly to the wafer surface. As a consequence the collection distance is decoupled from the wafer thickness resulting in a radiation hard pixel detector by design. Between 2010 and 2012, 3D silicon pixel detectors have undergone an intensive programme of beam test experiments. As a result, 3D silicon has successfully qualified for the ATLAS upgrade project, the Insertable B-Layer (IBL), which will be installed in the long-shutdown in 2013-14. This thesis presents selected results from these beam test studies with 3D sensors bonded to both current ATLAS readout cards (FE-I3) and newly developed readout cards for the IBL (FE-I4). 3D devices were studied using 4 GeV positrons at DESY and 120 GeV pions at the SPS at CERN. Measurements presented include tracking efficiency (of the whole sensor, the pixel and the area around the electrodes), studies of the active edge pixels of SINTEF devices and cluster size distributions as a function of incident angle for IBL 3D design sensors. A simulation of 3D silicon sensors in an antiproton beam test for the AEgIS experiment, with comparison to experimental results and a previous simulation, are also presented.

No description available.

<p>The high luminosity phase of the LHC, poised to start taking data in 2027, aims to increase the instantaneous luminosity of the machine to 7.5 x 10³⁴ cm^-2 s^-1. This will make it possible for experiments at CERN to make higher precision measurements on known physics phenomenon as well as to search for “new physics”. However, this motivates the need for hardware upgrades at the various experiments in order to ensure compatibility with the HL-LHC. This thesis describes some of the efforts to upgrade the inner-most layers of the Compact Muon Solenoid, namely the CMS silicon pixel tracking detector. </p> <p>Silicon sensors used to track particles are installed in the detector as part of a pixel sensor module. Modules consist of a silicon sensor-readout chip assembly that is wire-bonded to an HDI, or High Density Interconnects to provide power and signals. </p> <p>As part of the upgrade, 2,541 modules need to be assembled delicately and identically with alignment error margins as low as 10 microns. Assembly will be across three production sites in clean rooms to avoid dust and humidity contamination.</p> <p>In addition, the modules need to survive high magnetic fields and extended close-range radiation as part of the HL-LHC.</p> <p>In line with this effort, new materials and assembly procedures able to sustain such damage are investigated. Techniques to assemble modules are explored, specifically precision placing of parts with a robotic gantry and techniques to protect wirebonds. This is followed by a discussion of the accuracy and repeatability.</p>

This work investigates the optimal measurement matrices that can be used in compressive sensing (CS) image sensors. It also optimizes CMOS current-model pixel cell circuits for CS image sensors. Based on the outcomes from these optimization studies, three CS image senor circuits with compression ratios of 4, 6, and 8 are designed with using a 130 nm CMOS technology. The pixel arrays used in the image sensors has a size of 256X256. Circuit simulations with benchmark image Lenna show that the three images sensors can achieve peak signal to noise ratio (PSNR) values of 37.64, 33.29, and 32.44 dB respectively.

Project deals with the development of a 2D, roleplaying videogame for the computer platform. Theoretical part of the thesis is focused on background of pixelart in videogames, as well as game and storytelling cliche, while both of these aspects are used in the final project. Practical part is the design of characters, enviroment and scenes, and the complete realization of a prototype for pixelart videogame named ENOUGH, with the visual of retro games for old platforms. Its story is being shown as a cliche as well, though with the strong symbolism refering to authors psychique and on the mental health or memories.